Index: trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
===================================================================
--- trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp	(revision 31084)
+++ trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp	(revision 31085)
@@ -352,6 +352,6 @@
     uint32_t     au32Regs[113];
     /* Current BD index  */
-    uint32_t    u32Cvi; 
-    uint64_t    u64CviAddr; 
+    uint32_t    u32Cvi;
+    uint64_t    u64CviAddr;
     /* Length of current BD entry */
     uint32_t    u32CviLen;
@@ -577,5 +577,5 @@
 {
     bool fIrq = false;
-   /* @todo add state change */    
+   /* @todo add state change */
     if(   INTCTL_CIE(pState)
        && (   RIRBSTS_RINTFL(pState)
@@ -585,5 +585,5 @@
         fIrq = true;
     }
-    if (   INTCTL_SX(pState, 4) 
+    if (   INTCTL_SX(pState, 4)
         && SDSTS(pState, 4) && HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))
     {
@@ -677,5 +677,5 @@
 
     PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
-    
+
     rc = hdaCmdSync(pState, true);
     if (RT_FAILURE(rc))
@@ -800,5 +800,5 @@
     {
         /* enter reset state*/
-        if (   HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) 
+        if (   HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
             || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
         {
@@ -976,5 +976,5 @@
     }
 #endif
-    return VINF_SUCCESS; 
+    return VINF_SUCCESS;
 }
 DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
@@ -1084,5 +1084,5 @@
     uint8_t v = RIRBSTS(pState);
     RIRBSTS(pState) = (v ^ nv) & v;
-    
+
     return hdaProcessInterrupt(pState);
 }
@@ -1115,5 +1115,5 @@
 static void fetch_bd(INTELHDLinkState *pState)
 {
-    dump_bd(pState); 
+    dump_bd(pState);
     pState->u32Cvi;
     uint8_t  bdle[16];
@@ -1209,5 +1209,5 @@
                         }
                         if (pState->u32CviPos == pState->u32CviLen)
-                        { 
+                        {
                             pState->u32CviPos = 0;
                             pState->u32Cvi++;
@@ -1233,5 +1233,5 @@
  *
  * @note: while implementation was detected so called "forgotten" or "hole" registers
- * which description is missed in RPM, datasheet or spec. 
+ * which description is missed in RPM, datasheet or spec.
  *
  * @returns VBox status code.
@@ -1253,6 +1253,6 @@
         Log(("hda: access to registers except GCTL is blocked while reset\n"));
     }
-    Assert(   index != -1 
-           && u32Offset == s_ichIntelHDRegMap[index].offset 
+    Assert(   index != -1
+           && u32Offset == s_ichIntelHDRegMap[index].offset
            && cb <= 4);
     if (index != -1)
@@ -1262,8 +1262,8 @@
         switch(cb)
         {
-            case 1: mask = 0x000000ff; break; 
-            case 2: mask = 0x0000ffff; break; 
-            case 3: mask = 0x00ffffff; break; 
-            case 4: mask = 0xffffffff; break; 
+            case 1: mask = 0x000000ff; break;
+            case 2: mask = 0x0000ffff; break;
+            case 3: mask = 0x00ffffff; break;
+            case 4: mask = 0xffffffff; break;
         }
         Assert(u32Offset == s_ichIntelHDRegMap[index].offset);
@@ -1301,6 +1301,6 @@
         Log(("hda: access to registers except GCTL is blocked while reset\n"));
     }
-    Assert(   index != -1 
-           && u32Offset == s_ichIntelHDRegMap[index].offset 
+    Assert(   index != -1
+           && u32Offset == s_ichIntelHDRegMap[index].offset
            && cb <= 4);
     if (index != -1)
@@ -1311,10 +1311,10 @@
         switch(cb)
         {
-            case 1: mask = 0xffffff00; break; 
-            case 2: mask = 0xffff0000; break; 
-            case 3: mask = 0xff000000; break; 
-            case 4: mask = 0x00000000; break; 
+            case 1: mask = 0xffffff00; break;
+            case 2: mask = 0xffff0000; break;
+            case 3: mask = 0xff000000; break;
+            case 4: mask = 0x00000000; break;
         }
-        *(uint32_t *)pv = (v & mask) | (*(uint32_t *)pv & ~mask); 
+        *(uint32_t *)pv = (v & mask) | (*(uint32_t *)pv & ~mask);
         rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
         Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
@@ -1401,5 +1401,5 @@
         pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
 
-    /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20 
+    /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
      * bits are reserved for stream number 18.2.33 */
     SDCTL(&pThis->hda, 0) = 0x40000;
@@ -1421,5 +1421,5 @@
     SDFIFOS(&pThis->hda, 6) = 0xBF;
     SDFIFOS(&pThis->hda, 7) = 0xBF;
-    
+
     /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
     STATESTS(&pThis->hda) = 0x1;
@@ -1483,5 +1483,5 @@
     PCIDevSetBaseAddress        (&pThis->dev, 0,       /* 10 rw - MMIO */
                                  false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
-    /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for 
+    /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
        verb F20 should provide device/codec recognition. */
     PCIDevSetSubSystemVendorId  (&pThis->dev, 0x0000); /* 2c ro - intel.) */
@@ -1492,5 +1492,5 @@
 
     //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
-    // of these values needs to be properly documented! 
+    // of these values needs to be properly documented!
     /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
     pThis->dev.config[0x40] = 0x01;
@@ -1541,5 +1541,5 @@
     pThis->hda.Codec.pfnTransfer = hdaTransfer;
     pThis->hda.Codec.pfnReset = hdaCodecReset;
-    /* 
+    /*
      * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
      * hdaReset shouldn't affects these registers.
@@ -1557,5 +1557,5 @@
 {
     PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
-    
+
     int rc = stac9220Destruct(&pThis->hda.Codec);
     AssertRC(rc);
