VirtualBox

Changeset 31429 in vbox for trunk/src/VBox/Devices/Audio


Ignore:
Timestamp:
Aug 6, 2010 4:55:19 AM (14 years ago)
Author:
vboxsync
Message:

Audio/HDA: adds stream reset flag and behavior described in RPM(6.3.32). INTSTS is OR of other status registers (RPM 6.2.11).

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp

    r31378 r31429  
    381381    CODECState  Codec;
    382382    uint8_t     u8Counter;
     383    uint8_t     u8StreamsInReset;
    383384} INTELHDLinkState;
    384385
     
    428429DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    429430static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
     431static void fetch_bd(INTELHDLinkState *pState);
    430432
    431433/* see 302349 p 6.2*/
     
    462464    { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS"      , "Global Status" },
    463465    { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32          , hdaRegWriteU32          , "INTCTL"    , "Interrupt Control" },
    464     { 0x00024, 0x00004, 0xC00000FF, 0x400000FF, hdaRegReadINTSTS       , hdaRegWriteINTSTS       , "INTSTS"    , "Interrupt Status" },
     466    { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS       , hdaRegWriteUnimplemented, "INTSTS"    , "Interrupt Status" },
    465467    //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
    466468    { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK"    , "Wall Clock Counter" },
     
    582584    if(   INTCTL_CIE(pState)
    583585       && (   RIRBSTS_RINTFL(pState)
    584            ||  RIRBSTS_RIRBOIS(pState)))
    585     {
    586         INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, CIS);
     586           || RIRBSTS_RIRBOIS(pState))
     587           || STATESTS(pState))
     588    {
    587589        fIrq = true;
    588590    }
     
    590592        && SDSTS(pState, 4) && HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))
    591593    {
    592         INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, S4);
    593594        fIrq = true;
    594595    }
     
    875876DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    876877{
    877     uint32_t v = INTSTS(pState);
    878     v &= ~HDA_REG_FIELD_FLAG_MASK(INTSTS, GIS);
    879     v |= (v ? HDA_REG_FIELD_FLAG_MASK(INTSTS, GIS) : 0);
     878    uint32_t v = 0;
     879    if (   RIRBSTS_RIRBOIS(pState)
     880        || RIRBSTS_RINTFL(pState)
     881        || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
     882        || STATESTS(pState))
     883        v |= RT_BIT(30);
     884#define HDA_IS_STREAM_EVENT(pState, stream)             \
     885       (   (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))  \
     886        || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))  \
     887        || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
     888#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
     889    MARK_STREAM(pState, 0, v);
     890    MARK_STREAM(pState, 1, v);
     891    MARK_STREAM(pState, 2, v);
     892    MARK_STREAM(pState, 3, v);
     893    MARK_STREAM(pState, 4, v);
     894    MARK_STREAM(pState, 5, v);
     895    MARK_STREAM(pState, 6, v);
     896    MARK_STREAM(pState, 7, v);
     897    v |= v ? RT_BIT(31) : 0;
    880898    *pu32Value = v;
    881899    return VINF_SUCCESS;
    882 }
    883 
    884 DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    885 {
    886     uint32_t v = INTSTS(pState);
    887     INTSTS(pState) = (v ^ u32Value) & v;
    888     return hdaProcessInterrupt(pState);
    889900}
    890901
     
    942953    return hdaRegReadU24(pState, offset, index, pu32Value);
    943954}
    944 
     955#define HDA_STREAM_BITMASK(offset) (1 << (((offset) - 0x80) >> 5))
     956#define HDA_IS_STREAM_IN_RESET(pState, offset) ((pState)->u8StreamsInReset & HDA_STREAM_BITMASK((offset)))
    945957DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    946958{
    947     if((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)))
    948     {
     959    if(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))
     960    {
     961        LogRel(("hda: guest has iniated hw stream reset\n"));
     962        pState->u8StreamsInReset |= HDA_STREAM_BITMASK(offset);
    949963        hdaStreamReset(pState, offset);
     964        HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
     965    }
     966    else if (HDA_IS_STREAM_IN_RESET(pState, offset))
     967    {
     968        LogRel(("hda: guest has iniated exit of stream reset\n"));
     969        pState->u8StreamsInReset &= ~HDA_STREAM_BITMASK(offset);
     970        HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
    950971    }
    951972    /* @todo: use right offsets for right streams */
     
    957978        if (offset == 0x100)
    958979        {
     980            fetch_bd(pState);
    959981            AUD_set_active_out(pState->Codec.voice_po, 1);
    960982            //SDSTS(pState, 4) |= (1<<5);
     
    971993            AUD_set_active_out(pState->Codec.voice_po, 0);
    972994        }
    973         SSYNC(pState) &= ~(1<< (offset - 0x80));
     995        //SSYNC(pState) &= ~(1<< (offset - 0x80));
    974996    }
    975997    int rc = hdaRegWriteU24(pState, offset, index, u32Value);
     
    11811203    INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
    11821204    STATESTS(pState) |= 1 << (pCodecState->id);
    1183     INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, CIS);
    11841205    return VINF_SUCCESS;
    11851206}
     
    11991220                return;
    12001221            SDCTL(pState, 4) |= ((pState->Codec.pNodes[2].dac.u32F06_param & (0xf << 4)) >> 4) << 20;
    1201             fetch_bd(pState);
     1222            //fetch_bd(pState);
    12021223            while(   avail
    12031224                  && !fStop)
     
    12171238                    if (   SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)
    12181239                        && (   (   pState->u32CviPos == pState->u32CviLen
    1219                                 && pState->fCviIoc)
     1240                                && pState->fCviIoc )
    12201241                            || SDLPIB(pState, 4) == SDLCBL(pState, 4)))
    12211242                    {
    12221243                        SDSTS(pState,4) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
    1223                         INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, S4);
    12241244                        hdaProcessInterrupt(pState);
    12251245                        if (SDLPIB(pState, 4) == SDLCBL(pState, 4))
     
    12381258                    }
    12391259                    fStop = false;
     1260                    fetch_bd(pState);
    12401261                }
    1241                 fetch_bd(pState);
    12421262            }
    12431263        }
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