Changeset 31775 in vbox

Timestamp:

Aug 19, 2010 9:48:24 AM (15 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

64961

Message:

PGM: Wrap up all access to PAE/LM PTEs so that we can treat the invalid entries used by PGM_WITH_MMIO_OPTIMIZATIONS as not-present.

Location:

trunk/src/VBox/VMM

Files:

• PGM.cpp (modified) (3 diffs)
• PGMGstDefs.h (modified) (1 diff)
• PGMInternal.h (modified) (4 diffs)
• PGMMap.cpp (modified) (2 diffs)
• PGMPool.cpp (modified) (8 diffs)
• PGMShw.h (modified) (1 diff)
• VMMAll/PGMAllBth.h (modified) (57 diffs)
• VMMAll/PGMAllMap.cpp (modified) (3 diffs)
• VMMAll/PGMAllPool.cpp (modified) (41 diffs)
• VMMAll/PGMAllShw.h (modified) (8 diffs)
• VMMGC/PGMGCShw.h (modified) (1 diff)
• VMMRZ/PGMRZDynMap.cpp (modified) (1 diff)

trunk/src/VBox/VMM/PGM.cpp

@@ -3558 +3558 @@
  * @param   pHlp        Pointer to the output functions.
  */
-static int  pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
+static int  pgmR3DumpHierarchyHCPaePT(PVM pVM, PCPGMSHWPTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
 {
     for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
-    {
-        X86PTEPAE Pte = pPT->a[i];
-        if (Pte.n.u1Present)
+        if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
         {
+            X86PTEPAE Pte;
+            Pte.u = PGMSHWPTEPAE_GET_U(pPT->a[i]);
             pHlp->pfnPrintf(pHlp,
                             fLongMode       /*P R  S  A  D  G  WT CD AT NX 4M a p ?  */
@@ -3584 +3584 @@
                             Pte.u & X86_PTE_PAE_PG_MASK);
         }
-    }
     return VINF_SUCCESS;
 }
@@ -3659 +3658 @@
                 {
                     /** @todo what about using the page pool for mapping PTs? */
-                    uint64_t    u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
-                    RTHCPHYS    HCPhysPT     = Pde.u & X86_PDE_PAE_PG_MASK;
-                    PX86PTPAE   pPT          = NULL;
+                    uint64_t        u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
+                    RTHCPHYS        HCPhysPT     = Pde.u & X86_PDE_PAE_PG_MASK;
+                    PPGMSHWPTPAE    pPT          = NULL;
                     if (!(Pde.u & PGM_PDFLAGS_MAPPING))
-                        pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
+                        pPT = (PPGMSHWPTPAE)MMPagePhys2Page(pVM, HCPhysPT);
                     else
                     {

trunk/src/VBox/VMM/PGMGstDefs.h

@@ -73 +73 @@
 #  define BTH_IS_NP_ACTIVE(pVM)                 (true)
 # else
-#  define GSTPT                                 SHWPT
-#  define PGSTPT                                PSHWPT
-#  define GSTPTE                                SHWPTE
-#  define PGSTPTE                               PSHWPTE
-#  define GSTPD                                 SHWPD
-#  define PGSTPD                                PSHWPD
-#  define GSTPDE                                SHWPDE
-#  define PGSTPDE                               PSHWPDE
-#  define GST_PTE_PG_MASK                       SHW_PTE_PG_MASK
+#  if PGM_SHW_TYPE == PGM_TYPE_32BIT /* Same as shadow paging, but no PGMSHWPTEPAE. */
+#   define GSTPT                                X86PT
+#   define PGSTPT                               PX86PT
+#   define GSTPTE                               X86PTE
+#   define PGSTPTE                              PX86PTE
+#   define GSTPD                                X86PD
+#   define PGSTPD                               PX86PD
+#   define GSTPDE                               X86PDE
+#   define PGSTPDE                              PX86PDE
+#   define GST_PTE_PG_MASK                      X86_PTE_PG_MASK
+#  else
+#   define GSTPT                                X86PTPAE
+#   define PGSTPT                               PX86PTPAE
+#   define GSTPTE                               X86PTEPAE
+#   define PGSTPTE                              PX86PTEPAE
+#   define GSTPD                                X86PDPAE
+#   define PGSTPD                               PX86PDPAE
+#   define GSTPDE                               X86PDEPAE
+#   define PGSTPDE                              PX86PDEPAE
+#   define GST_PTE_PG_MASK                      X86_PTE_PAE_PG_MASK
+#  endif
 #  define GST_IS_NX_ACTIVE(pVCpu)               (pgmGstIsNoExecuteActive(pVCpu))
 #  if PGM_GST_TYPE == PGM_TYPE_PROT             /* (comment at top of PGMAllBth.h) */

trunk/src/VBox/VMM/PGMInternal.h

@@ -413 +413 @@
 # define PGM_INVL_ALL_VCPU_TLBS(pVM)            HWACCMFlushTLBOnAllVCpus(pVM)
 #endif
+
+
+/** @name Safer Shadow PAE PT/PTE
+ * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
+ * present.
+ *
+ * @{
+ */
+#if 1
+/**
+ * For making sure that u1Present and X86_PTE_P checks doesn't mistake
+ * invalid entries for present.
+ * @sa X86PTEPAE.
+ */
+typedef union PGMSHWPTEPAE
+{
+    /** Unsigned integer view */
+    X86PGPAEUINT    uCareful;
+#if 0
+    /* Not bit field view. */
+    /** 32-bit view. */
+    uint32_t        au32[2];
+    /** 16-bit view. */
+    uint16_t        au16[4];
+    /** 8-bit view. */
+    uint8_t         au8[8];
+#endif
+} PGMSHWPTEPAE;
+
+# define PGMSHWPTEPAE_IS_P(Pte)                 ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
+# define PGMSHWPTEPAE_IS_RW(Pte)                ( !!((Pte).uCareful & X86_PTE_RW))
+# define PGMSHWPTEPAE_IS_US(Pte)                ( !!((Pte).uCareful & X86_PTE_US))
+# define PGMSHWPTEPAE_IS_A(Pte)                 ( !!((Pte).uCareful & X86_PTE_A))
+# define PGMSHWPTEPAE_IS_D(Pte)                 ( !!((Pte).uCareful & X86_PTE_D))
+# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)       ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
+# define PGMSHWPTEPAE_IS_P_RW(Pte)              ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
+# define PGMSHWPTEPAE_GET_LOG(Pte)              ( (Pte).uCareful )
+# define PGMSHWPTEPAE_GET_HCPHYS(Pte)           ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
+# define PGMSHWPTEPAE_GET_U(Pte)                ( (Pte).uCareful ) /**< Use with care. */
+# define PGMSHWPTEPAE_SET(Pte, uVal)            do { (Pte).uCareful = (uVal); } while (0)
+# define PGMSHWPTEPAE_SET2(Pte, Pte2)           do { (Pte).uCareful = (Pte2).uCareful; } while (0)
+# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal)     do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
+# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)    do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
+# define PGMSHWPTEPAE_SET_RO(Pte)               do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
+# define PGMSHWPTEPAE_SET_RW(Pte)               do { (Pte).uCareful |= X86_PTE_RW; } while (0)
+
+/**
+ * For making sure that u1Present and X86_PTE_P checks doesn't mistake
+ * invalid entries for present.
+ * @sa X86PTPAE.
+ */
+typedef struct PGMSHWPTPAE
+{
+    PGMSHWPTEPAE  a[X86_PG_PAE_ENTRIES];
+} PGMSHWPTPAE;
+
+#else
+typedef X86PTEPAE           PGMSHWPTEPAE;
+typedef X86PTPAE            PGMSHWPTPAE;
+# define PGMSHWPTEPAE_IS_P(Pte)                 ( (Pte).n.u1Present )
+# define PGMSHWPTEPAE_IS_RW(Pte)                ( (Pte).n.u1Write )
+# define PGMSHWPTEPAE_IS_US(Pte)                ( (Pte).n.u1User )
+# define PGMSHWPTEPAE_IS_A(Pte)                 ( (Pte).n.u1Accessed )
+# define PGMSHWPTEPAE_IS_D(Pte)                 ( (Pte).n.u1Dirty )
+# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)       ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
+# define PGMSHWPTEPAE_IS_P_RW(Pte)              ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
+# define PGMSHWPTEPAE_GET_LOG(Pte)              ( (Pte).u )
+# define PGMSHWPTEPAE_GET_HCPHYS(Pte)           ( (Pte).u & X86_PTE_PAE_PG_MASK )
+# define PGMSHWPTEPAE_GET_U(Pte)                ( (Pte).u ) /**< Use with care. */
+# define PGMSHWPTEPAE_SET(Pte, uVal)            do { (Pte).u = (uVal); } while (0)
+# define PGMSHWPTEPAE_SET2(Pte, Pte2)           do { (Pte).u = (Pte2).u; } while (0)
+# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal)     do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
+# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)    do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
+# define PGMSHWPTEPAE_SET_RO(Pte)               do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
+# define PGMSHWPTEPAE_SET_RW(Pte)               do { (Pte).u |= X86_PTE_RW; } while (0)
+
+#endif
+
+/** Pointer to a shadow PAE PTE.  */
+typedef PGMSHWPTEPAE       *PPGMSHWPTEPAE;
+/** Pointer to a const shadow PAE PTE.  */
+typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
+
+/** Pointer to a shadow PAE page table.  */
+typedef PGMSHWPTPAE        *PPGMSHWPTPAE;
+/** Pointer to a const shadow PAE page table.  */
+typedef PGMSHWPTPAE const  *PCPGMSHWPTPAE;
+/** @}  */
+
 
 /** Size of the GCPtrConflict array in PGMMAPPING.
@@ -467 +556 @@
         R3PTRTYPE(PX86PT)               pPTR3;
         /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
-        R3PTRTYPE(PX86PTPAE)            paPaePTsR3;
+        R3PTRTYPE(PPGMSHWPTPAE)         paPaePTsR3;
         /** The RC virtual address of the 32-bit page table. */
         RCPTRTYPE(PX86PT)               pPTRC;
         /** The RC virtual address of the two PAE page table. */
-        RCPTRTYPE(PX86PTPAE)            paPaePTsRC;
+        RCPTRTYPE(PPGMSHWPTPAE)         paPaePTsRC;
         /** The R0 virtual address of the 32-bit page table. */
         R0PTRTYPE(PX86PT)               pPTR0;
         /** The R0 virtual address of the two PAE page table. */
-        R0PTRTYPE(PX86PTPAE)            paPaePTsR0;
+        R0PTRTYPE(PPGMSHWPTPAE)         paPaePTsR0;
     } aPTs[1];
 } PGMMAPPING;
@@ -2318 +2407 @@
  * PGMPOOL_TD_CREFS_SHIFT. */
 #define PGMPOOL_TD_CREFS_MASK           0x3
-/** The cRef value used to indiciate that the idx is the head of a
+/** The cRefs value used to indiciate that the idx is the head of a
  * physical cross reference list. */
 #define PGMPOOL_TD_CREFS_PHYSEXT        PGMPOOL_TD_CREFS_MASK
@@ -2917 +3006 @@
     RCPTRTYPE(PX86PTE)              paDynPageMap32BitPTEsGC;
     /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
-    RCPTRTYPE(PX86PTEPAE)           paDynPageMapPaePTEsGC;
+    RCPTRTYPE(PPGMSHWPTEPAE)        paDynPageMapPaePTEsGC;
 
 

trunk/src/VBox/VMM/PGMMap.cpp

@@ -172 +172 @@
         pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
         pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
-        pNew->aPTs[i].paPaePTsR3 = (PX86PTPAE)pbPTs;
+        pNew->aPTs[i].paPaePTsR3 = (PPGMSHWPTPAE)pbPTs;
         pNew->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pbPTs);
         pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
@@ -1405 +1405 @@
             while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
             {
-                if (!CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].n.u1Present)
+                PCPGMSHWPTEPAE pPte = &pCur->aPTs[iPT].CTXALLSUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
+                if (!PGMSHWPTEPAE_IS_P(*pPte))
                     return VERR_PAGE_NOT_PRESENT;
-                RTHCPHYS HCPhys = CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].u & X86_PTE_PAE_PG_MASK;
+                RTHCPHYS HCPhys = PGMSHWPTEPAE_GET_HCPHYS(*pPte);
 
                 /*

trunk/src/VBox/VMM/PGMPool.cpp

@@ -650 +650 @@
                             {
                                 bool fFoundFirst = false;
-                                PX86PTPAE pPT = (PX86PTPAE)pvShw;
+                                PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)pvShw;
                                 for (unsigned ptIndex = 0; ptIndex < RT_ELEMENTS(pPT->a); ptIndex++)
                                 {
@@ -662 +662 @@
                                             fFoundFirst = true;
                                         }
-                                        if (pPT->a[ptIndex].n.u1Present)
+                                        if (PGMSHWPTEPAE_IS_P(pPT->a[ptIndex]))
                                         {
-                                            pgmPoolTracDerefGCPhysHint(pPool, pPage, pPT->a[ptIndex].u & X86_PTE_PAE_PG_MASK, NIL_RTGCPHYS);
+                                            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pPT->a[ptIndex]), NIL_RTGCPHYS);
                                             if (pPage->iFirstPresent == ptIndex)
                                                 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
@@ -848 +848 @@
         if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
         {
-            PX86PTPAE pShwPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
+            PPGMSHWPTPAE pShwPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
             {
                 PX86PTPAE pGstPT;
@@ -857 +857 @@
                 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
                 {
-                    if (pShwPT->a[j].n.u1Present)
+                    if (PGMSHWPTEPAE_IS_P(pShwPT->a[j]))
                     {
                         RTHCPHYS HCPhys = NIL_RTHCPHYS;
                         rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[j].u & X86_PTE_PAE_PG_MASK, &HCPhys);
-                        if (    rc != VINF_SUCCESS
-                            ||  (pShwPT->a[j].u & X86_PTE_PAE_PG_MASK) != HCPhys)
+                        if (   rc != VINF_SUCCESS
+                            || PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[j]) != HCPhys)
                         {
                             if (fFirstMsg)
@@ -869 +869 @@
                                 fFirstMsg = false;
                             }
-                            pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Mismatch HCPhys: rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, j, pGstPT->a[j].u, pShwPT->a[j].u, HCPhys);
+                            pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Mismatch HCPhys: rc=%Rrc idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, j, pGstPT->a[j].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), HCPhys);
                         }
-                        else
-                        if (    pShwPT->a[j].n.u1Write
-                            &&  !pGstPT->a[j].n.u1Write)
+                        else if (   PGMSHWPTEPAE_IS_RW(pShwPT->a[j])
+                                 && !pGstPT->a[j].n.u1Write)
                         {
                             if (fFirstMsg)
@@ -880 +879 @@
                                 fFirstMsg = false;
                             }
-                            pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Mismatch r/w gst/shw: idx=%d guest %RX64 shw=%RX64 vs %RHp\n", j, pGstPT->a[j].u, pShwPT->a[j].u, HCPhys);
+                            pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Mismatch r/w gst/shw: idx=%d guest %RX64 shw=%RX64 vs %RHp\n", j, pGstPT->a[j].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), HCPhys);
                         }
                     }
@@ -899 +898 @@
                     if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
                     {
-                        PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pTempPage);
+                        PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pTempPage);
 
                         for (unsigned k = 0; k < RT_ELEMENTS(pShwPT->a); k++)
                         {
-                            if (    pShwPT2->a[k].n.u1Present
-                                &&  pShwPT2->a[k].n.u1Write
+                            if (    PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[k])
 # ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
                                 &&  !pPage->fDirty
 # endif
-                                &&  ((pShwPT2->a[k].u & X86_PTE_PAE_PG_MASK) == HCPhysPT))
+                                &&  PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[k]) == HCPhysPT)
                             {
                                 if (fFirstMsg)
@@ -915 +913 @@
                                     fFirstMsg = false;
                                 }
-                                pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Mismatch: r/w: GCPhys=%RGp idx=%d shw %RX64 %RX64\n", pTempPage->GCPhys, k, pShwPT->a[k].u, pShwPT2->a[k].u);
+                                pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Mismatch: r/w: GCPhys=%RGp idx=%d shw %RX64 %RX64\n", pTempPage->GCPhys, k, PGMSHWPTEPAE_GET_LOG(pShwPT->a[k]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[k]));
                             }
                         }

trunk/src/VBox/VMM/PGMShw.h

@@ -79 +79 @@
 
 #else
-# define SHWPT                  X86PTPAE
-# define PSHWPT                 PX86PTPAE
-# define SHWPTE                 X86PTEPAE
-# define PSHWPTE                PX86PTEPAE
+# define SHWPT                  PGMSHWPTPAE
+# define PSHWPT                 PPGMSHWPTPAE
+# define SHWPTE                 PGMSHWPTEPAE
+# define PSHWPTE                PPGMSHWPTEPAE
 # define SHWPD                  X86PDPAE
 # define PSHWPD                 PX86PDPAE

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -1444 +1444 @@
  * @param   pPage       The page in question.
  * @param   fPteSrc     The flags of the source PTE.
- * @param   pPteDst     The shadow PTE (output).
+ * @param   pPteDst     The shadow PTE (output).  This is temporary storage and
+ *                      does not need to be set atomically.
  */
 DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint32_t fPteSrc, PSHWPTE pPteDst)
@@ -1461 +1462 @@
         /* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
 #else
-        pPteDst->u = (fPteSrc & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
-                   | PGM_PAGE_GET_HCPHYS(pPage);
+        SHW_PTE_SET(*pPteDst,
+                      (fPteSrc & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
+                    | PGM_PAGE_GET_HCPHYS(pPage));
 #endif
     }
@@ -1487 +1489 @@
 #  else
         /* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64).  */
-        pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg | X86_PTE_PAE_MBZ_MASK_NO_NX | X86_PTE_P;
+        SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg | X86_PTE_PAE_MBZ_MASK_NO_NX | X86_PTE_P);
 #  endif
     }
@@ -1495 +1497 @@
     {
         LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
-        pPteDst->u = 0;
+        SHW_PTE_SET(*pPteDst, 0);
     }
     /** @todo count these kinds of entries. */
@@ -1550 +1552 @@
             if (PGM_PAGE_IS_BALLOONED(pPage))
             {
-                Assert(!pPteDst->n.u1Present); /** @todo user tracking needs updating if this triggers. */
+                Assert(!SHW_PTE_IS_P(*pPteDst)); /** @todo user tracking needs updating if this triggers. */
                 return;
             }
@@ -1595 +1597 @@
                     LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
                     STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
-                    PteDst.u = 0;
+                    SHW_PTE_SET(PteDst, 0);
                 }
                 /*
@@ -1604 +1606 @@
                 {
                     STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
-                    PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
-                             | PGM_PAGE_GET_HCPHYS(pPage)
-                             | PGM_PTFLAGS_TRACK_DIRTY;
+                    SHW_PTE_SET(PteDst,
+                                  (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
+                                | PGM_PAGE_GET_HCPHYS(pPage)
+                                | PGM_PTFLAGS_TRACK_DIRTY);
                 }
                 else
@@ -1621 +1624 @@
                     /* PteDst.n.u1Size = 0 */
 #else
-                    PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
-                             | PGM_PAGE_GET_HCPHYS(pPage);
+                    SHW_PTE_SET(PteDst,
+                                  (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
+                                | PGM_PAGE_GET_HCPHYS(pPage));
 #endif
                 }
@@ -1629 +1633 @@
                  * Make sure only allocated pages are mapped writable.
                  */
-                if (    PteDst.n.u1Write
-                    &&  PteDst.n.u1Present
+                if (    SHW_PTE_IS_P_RW(PteDst)
                     &&  PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
                 {
                     /* Still applies to shared pages. */
                     Assert(!PGM_PAGE_IS_ZERO(pPage));
-                    PteDst.n.u1Write = 0;   /** @todo this isn't quite working yet. Why, isn't it? */
+                    SHW_PTE_SET_RO(PteDst);   /** @todo this isn't quite working yet. Why, isn't it? */
                     Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
                 }
@@ -1643 +1646 @@
              * Keep user track up to date.
              */
-            if (PteDst.n.u1Present)
+            if (SHW_PTE_IS_P(PteDst))
             {
-                if (!pPteDst->n.u1Present)
+                if (!SHW_PTE_IS_P(*pPteDst))
                     PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
-                else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
+                else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
                 {
-                    Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
-                    PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK, iPTDst);
+                    Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(*pPteDst), SHW_PTE_LOG64(PteDst)));
+                    PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
                     PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
                 }
             }
-            else if (pPteDst->n.u1Present)
+            else if (SHW_PTE_IS_P(*pPteDst))
             {
-                Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
-                PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK, iPTDst);
+                Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", SHW_PTE_LOG64(*pPteDst)));
+                PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
             }
 
@@ -1667 +1670 @@
                 pShwPage->fSeenNonGlobal = true;
 #endif
-            ASMAtomicWriteSize(pPteDst, PteDst.u);
+            SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
             return;
         }
@@ -1683 +1686 @@
      * an empty entry, making sure to keep the user tracking up to date.
      */
-    if (pPteDst->n.u1Present)
-    {
-        Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
-        PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK, iPTDst);
-    }
-    ASMAtomicWriteSize(pPteDst, 0);
+    if (SHW_PTE_IS_P(*pPteDst))
+    {
+        Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", SHW_PTE_LOG64(*pPteDst)));
+        PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
+    }
+    SHW_PTE_ATOMIC_SET(*pPteDst, 0);
 }
 
@@ -1862 +1865 @@
                         for (; iPTDst < iPTDstEnd; iPTDst++)
                         {
-                            if (!pPTDst->a[iPTDst].n.u1Present)
+                            if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
                             {
                                 GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
@@ -1887 +1890 @@
                                       PteSrc.n.u1User & PdeSrc.n.u1User,
                                       (uint64_t)PteSrc.u,
-                                      (uint64_t)pPTDst->a[iPTDst].u,
-                                      pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
+                                      SHW_PTE_LOG64(pPTDst->a[iPTDst]),
+                                      SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
                             }
                         }
@@ -1904 +1907 @@
                               PteSrc.n.u1User & PdeSrc.n.u1User,
                               (uint64_t)PteSrc.u,
-                              (uint64_t)pPTDst->a[iPTDst].u,
-                              pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
+                              SHW_PTE_LOG64(pPTDst->a[iPTDst]),
+                              SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
                     }
                 }
@@ -1911 +1914 @@
                 {
                     LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
-                    Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
+                    Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
                 }
             }
@@ -1960 +1963 @@
                                                      &PteDst);
                     else
-                        PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
-                                 | PGM_PAGE_GET_HCPHYS(pPage);
+                        SHW_PTE_SET(PteDst,
+                                      (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
+                                    | PGM_PAGE_GET_HCPHYS(pPage));
 
                     const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
-                    if (    PteDst.n.u1Present
-                        &&  !pPTDst->a[iPTDst].n.u1Present)
+                    if (    SHW_PTE_IS_P(PteDst)
+                        &&  !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
                         PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
 
                     /* Make sure only allocated pages are mapped writable. */
-                    if (    PteDst.n.u1Write
-                        &&  PteDst.n.u1Present
+                    if (    SHW_PTE_IS_P_RW(PteDst)
                         &&  PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
                     {
                         /* Still applies to shared pages. */
                         Assert(!PGM_PAGE_IS_ZERO(pPage));
-                        PteDst.n.u1Write = 0;   /** @todo this isn't quite working yet... */
+                        SHW_PTE_SET_RO(PteDst);   /** @todo this isn't quite working yet... */
                         Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
                     }
 
-                    ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
+                    SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
 
                     /*
@@ -2128 +2131 @@
         for (; iPTDst < iPTDstEnd; iPTDst++)
         {
-            if (!pPTDst->a[iPTDst].n.u1Present)
+            if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
             {
                 RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT);
@@ -2152 +2155 @@
                       PteSrc.n.u1User & PdeSrc.n.u1User,
                       (uint64_t)PteSrc.u,
-                      (uint64_t)pPTDst->a[iPTDst].u,
-                      pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
+                      SHW_PTE_LOG64(pPTDst->a[iPTDst]),
+                      SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
 
                 if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
@@ -2159 +2162 @@
             }
             else
-                Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
+                Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
         }
     }
@@ -2191 +2194 @@
               PteSrc.n.u1User & PdeSrc.n.u1User,
               (uint64_t)PteSrc.u,
-              (uint64_t)pPTDst->a[iPTDst].u,
-              pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
+              SHW_PTE_LOG64(pPTDst->a[iPTDst]),
+              SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
     }
     return VINF_SUCCESS;
@@ -2325 +2328 @@
                 PSHWPT      pPTDst   = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
                 PSHWPTE     pPteDst  = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
-                if (    pPteDst->n.u1Present
-                    &&  pPteDst->n.u1Write)
+                if (SHW_PTE_IS_P_RW(*pPteDst))
                 {
                     /* Stale TLB entry. */
@@ -2373 +2375 @@
             PSHWPT      pPTDst   = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
             PSHWPTE     pPteDst  = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
-            if (pPteDst->n.u1Present)    /** @todo Optimize accessed bit emulation? */
+            if (SHW_PTE_IS_P(*pPteDst))    /** @todo Optimize accessed bit emulation? */
             {
-                if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
+                if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
                 {
                     PPGMPAGE pPage  = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
@@ -2396 +2398 @@
                             Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
                             /* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
-                            PteDst.n.u1Write = 0;
+                            SHW_PTE_SET_RO(PteDst);
                         }
                         else
@@ -2407 +2409 @@
                             }
                             if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
-                                PteDst.n.u1Write = 1;
+                                SHW_PTE_SET_RW(PteDst);
                             else
                             {
                                 /* Still applies to shared pages. */
                                 Assert(!PGM_PAGE_IS_ZERO(pPage));
-                                PteDst.n.u1Write = 0;
+                                SHW_PTE_SET_RO(PteDst);
                             }
                         }
                     }
                     else
-                        PteDst.n.u1Write = 1;  /** @todo r=bird: This doesn't make sense to me. */
-
-                    PteDst.n.u1Dirty    = 1;
-                    PteDst.n.u1Accessed = 1;
-                    PteDst.au32[0]     &= ~PGM_PTFLAGS_TRACK_DIRTY;
-                    ASMAtomicWriteSize(pPteDst, PteDst.u);
+                        SHW_PTE_SET_RW(PteDst);  /** @todo r=bird: This doesn't make sense to me. */
+
+                    SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) | X86_PTE_D | X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
+                    SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
                     PGM_INVL_PG(pVCpu, GCPtrPage);
                     return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;    /* restarts the instruction. */
@@ -2430 +2430 @@
                 /* Check for stale TLB entry; only applies to the SMP guest case. */
                 if (    pVM->cCpus > 1
-                    &&  pPteDst->n.u1Write == 1
-                    &&  pPteDst->n.u1Accessed == 1)
+                    &&  SHW_PTE_IS_RW(*pPteDst)
+                    &&  SHW_PTE_IS_A(*pPteDst))
                 {
                     /* Stale TLB entry. */
@@ -2739 +2739 @@
                               PteSrc.n.u1User & PdeSrc.n.u1User,
                               (uint64_t)PteSrc.u,
-                              pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
+                              SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
                               (RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
                     }
@@ -2792 +2792 @@
             /* Get address and flags from the source PDE. */
             SHWPTE PteDstBase;
-            PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
+            SHW_PTE_SET(PteDstBase, PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT));
 
             /* Loop thru the entries in the shadow PT. */
@@ -2820 +2820 @@
                         if (    PGM_PAGE_GET_TYPE(pPage)  == PGMPAGETYPE_RAM
                             &&  (   PGM_PAGE_IS_ZERO(pPage)
-                                 || (   PteDstBase.n.u1Write
+                                 || (   SHW_PTE_IS_RW(PteDstBase)
                                      && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
 #  ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
@@ -2841 +2841 @@
                         if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
                         {
+/** @todo call SyncHandlerPte !!
+ *  FIXME FIXME FIXME */
                             if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
                             {
-                                PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
-                                PteDst.n.u1Write = 0;
+                                SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) | SHW_PTE_GET_U(PteDstBase));
+                                SHW_PTE_SET_RO(PteDst);
                             }
                             else
-                                PteDst.u = 0;
+                                SHW_PTE_SET(PteDst, 0);
                         }
                         else if (PGM_PAGE_IS_BALLOONED(pPage))
-                        {
-                            /* Skip ballooned pages. */
-                            PteDst.u = 0;
-                        }
+                            SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
 # ifndef IN_RING0
                         /*
@@ -2862 +2861 @@
                         else if (    !PdeSrc.n.u1User
                                  &&  CSAMDoesPageNeedScanning(pVM, GCPtr | (iPTDst << SHW_PT_SHIFT)))
-                            PteDst.u = 0;
+                            SHW_PTE_SET(PteDst, 0);
 # endif
                         else
-                            PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
+                            SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) | SHW_PTE_GET_U(PteDstBase));
 
                         /* Only map writable pages writable. */
-                        if (    PteDst.n.u1Write
-                            &&  PteDst.n.u1Present
+                        if (    SHW_PTE_IS_P_RW(PteDst)
                             &&  PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
                         {
                             /* Still applies to shared pages. */
                             Assert(!PGM_PAGE_IS_ZERO(pPage));
-                            PteDst.n.u1Write = 0;   /** @todo this isn't quite working yet... */
+                            SHW_PTE_SET_RO(PteDst);   /** @todo this isn't quite working yet... */
                             Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))));
                         }
 
-                        if (PteDst.n.u1Present)
+                        if (SHW_PTE_IS_P(PteDst))
                             PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
 
-                        /* commit it */
+                        /* commit it (not atomic, new table) */
                         pPTDst->a[iPTDst] = PteDst;
                         Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
-                              (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
-                              PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
+                              (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
+                              SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
 
                         /* advance */
@@ -2899 +2897 @@
                     do
                     {
-                        pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
+                        SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
                         GCPhys += PAGE_SIZE;
                         iPTDst++;
@@ -2909 +2907 @@
                     Log(("Invalid pages at %RGp (2)\n", GCPhys));
                     for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
-                        pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
+                        SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
                 }
             } /* while more PTEs */
@@ -3930 +3928 @@
                             const SHWPTE PteDst = pPTDst->a[iPT];
 
-                            /* skip not-present entries. */
-                            if (!(PteDst.u & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
+                            /* skip not-present and dirty tracked entries. */
+                            if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
                                 continue;
-                            Assert(PteDst.n.u1Present);
+                            Assert(SHW_PTE_IS_P(PteDst));
 
                             const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
@@ -3943 +3941 @@
 # endif
                                 AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
-                                                GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
+                                                GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
                                                 (PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
                                 cErrors++;
@@ -3955 +3953 @@
 
                             /* match the physical addresses */
-                            HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
+                            HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
                             GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
 
@@ -3965 +3963 @@
                                 {
                                     AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                    GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                     GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                     cErrors++;
                                     continue;
@@ -3973 +3971 @@
                             {
                                 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                 cErrors++;
                                 continue;
@@ -3986 +3984 @@
                                 {
                                     AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                    GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                     GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                     cErrors++;
                                     continue;
                                 }
 # endif
-                                if (PteDst.n.u1Write)
+                                if (SHW_PTE_IS_RW(PteDst))
                                 {
                                     AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                    GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                     GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                     cErrors++;
                                 }
@@ -4002 +4000 @@
                             {
                                 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                 cErrors++;
                                 continue;
@@ -4012 +4010 @@
                                 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
                                 {
-                                    if (PteDst.n.u1Write)
+                                    if (SHW_PTE_IS_RW(PteDst))
                                     {
                                         AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                         continue;
@@ -4023 +4021 @@
                                 else
                                 {
-                                    if (   PteDst.n.u1Present
+                                    if (   SHW_PTE_IS_P(PteDst)
 # if PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
                                         && !PGM_PAGE_IS_MMIO(pPhysPage)
@@ -4030 +4028 @@
                                     {
                                         AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                         continue;
@@ -4041 +4039 @@
                                 if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
                                 {
-                                    if (PteDst.n.u1Write)
+                                    if (SHW_PTE_IS_RW(PteDst))
                                     {
                                         AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                         continue;
                                     }
-                                    if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
+                                    if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
                                     {
                                         AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                         continue;
                                     }
-                                    if (PteDst.n.u1Dirty)
+                                    if (SHW_PTE_IS_D(PteDst))
                                     {
                                         AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                     }
@@ -4065 +4063 @@
                                     {
                                         AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                        GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                     }
@@ -4073 +4071 @@
 # endif
                                 }
-                                else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
+                                else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
                                 {
                                     /* access bit emulation (not implemented). */
-                                    if (PteSrc.n.u1Accessed || PteDst.n.u1Present)
+                                    if (PteSrc.n.u1Accessed || SHW_PTE_IS_P(PteDst))
                                     {
                                         AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                         continue;
                                     }
-                                    if (!PteDst.n.u1Accessed)
+                                    if (!SHW_PTE_IS_A(PteDst))
                                     {
                                         AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                     }
@@ -4096 +4094 @@
                             }
 
-                            if (    (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
-                                &&  (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
+                            if (    (PteSrc.u & ~fIgnoreFlags)                != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
+                                &&  (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
                             )
                             {
                                 AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
-                                                GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
-                                                fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
+                                                 GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
+                                                 fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
                                 cErrors++;
                                 continue;
@@ -4176 +4174 @@
                             const SHWPTE PteDst = pPTDst->a[iPT];
 
-                            if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
+                            if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
                             {
                                 AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                 GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                 cErrors++;
                             }
 
                             /* skip not-present entries. */
-                            if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
+                            if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
                                 continue;
 
@@ -4190 +4188 @@
 
                             /* match the physical addresses */
-                            HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
+                            HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
 
 # ifdef IN_RING3
@@ -4199 +4197 @@
                                 {
                                     AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                    GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                     GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                     cErrors++;
                                 }
@@ -4206 +4204 @@
                             {
                                 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                 cErrors++;
                                 continue;
@@ -4218 +4216 @@
                                 {
                                     AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                    GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                     GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                     cErrors++;
                                     continue;
                                 }
 # endif
-                                if (PteDst.n.u1Write)
+                                if (SHW_PTE_IS_RW(PteDst))
                                 {
                                     AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                    GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                     GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                     cErrors++;
                                 }
@@ -4234 +4232 @@
                             {
                                 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                 GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                 cErrors++;
                                 continue;
@@ -4246 +4244 @@
                                     if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
                                     {
-                                        if (PteDst.n.u1Write)
+                                        if (SHW_PTE_IS_RW(PteDst))
                                         {
                                             AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                            GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                             GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                             cErrors++;
                                             continue;
@@ -4258 +4256 @@
                                 else
                                 {
-                                    if (   PteDst.n.u1Present
+                                    if (   SHW_PTE_IS_P(PteDst)
 # if PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
                                         && !PGM_PAGE_IS_MMIO(pPhysPage)
@@ -4265 +4263 @@
                                     {
                                         AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                        GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                         GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                         cErrors++;
                                         continue;
@@ -4273 +4271 @@
                             }
 
-                            if (    (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
-                                &&  (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
+                            if (    (PdeSrc.u & ~fIgnoreFlags)                != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
+                                &&  (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
                             )
                             {
                                 AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
-                                                GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
-                                                fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
+                                                 GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
+                                                 fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
                                 cErrors++;
                                 continue;

trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp

@@ -90 +90 @@
 
                 /* pae */
-                pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512].u = Pte.u;
+                PGMSHWPTEPAE_SET(pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512], Pte.u);
 
                 /* next */
@@ -144 +144 @@
      * Validate input.
      */
-    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
+    AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));
     Assert(cb);
 
@@ -182 +182 @@
 
                     /* PAE */
-                    pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u &= fMask | X86_PTE_PAE_PG_MASK;
-                    pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u |= fFlags & ~X86_PTE_PAE_PG_MASK;
+                    PPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
+                    PGMSHWPTEPAE_SET(*pPtePae,
+                                       (  PGMSHWPTEPAE_GET_U(*pPtePae)
+                                        & (fMask | X86_PTE_PAE_PG_MASK))
+                                     | (fFlags & ~(X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)));
 
                     /* invalidate tls */

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -39 +39 @@
 #include <iprt/asm-amd64-x86.h>
 #include <iprt/string.h>
-
-
-/*******************************************************************************
-*   Defined Constants And Macros                                               *
-*******************************************************************************/
-/**
- * Checks if a PAE PTE entry is actually present and not just invalid because
- * of the MMIO optimization.
- * @todo Move this to PGMInternal.h if necessary.
- */
-#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
-# define PGM_POOL_IS_PAE_PTE_PRESENT(Pte) \
-    ( ((Pte).u & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P)
-#else
-# define PGM_POOL_IS_PAE_PTE_PRESENT(Pte) \
-    ( (Pte).n.u1Present )
-#endif
-
-/**
- * Checks if a EPT PTE entry is actually present and not just invalid
- * because of the MMIO optimization.
- * @todo Move this to PGMInternal.h if necessary.
- */
-#define PGM_POOL_IS_EPT_PTE_PRESENT(Pte) \
-    ( (Pte).n.u1Present )
 
 
@@ -83 +58 @@
 #endif
 #if defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)
-static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT);
+static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT);
 #endif
 
@@ -209 +184 @@
        union
         {
-            void       *pv;
-            PX86PT      pPT;
-            PX86PTPAE   pPTPae;
-            PX86PD      pPD;
-            PX86PDPAE   pPDPae;
-            PX86PDPT    pPDPT;
-            PX86PML4    pPML4;
+            void           *pv;
+            PX86PT          pPT;
+            PPGMSHWPTPAE    pPTPae;
+            PX86PD          pPD;
+            PX86PDPAE       pPDPae;
+            PX86PDPT        pPDPT;
+            PX86PML4        pPML4;
         } uShw;
 
@@ -254 +229 @@
                     const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
                     LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
-                    if (PGM_POOL_IS_PAE_PTE_PRESENT(uShw.pPTPae->a[iShw]))
+                    if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
                     {
                         X86PTE GstPte;
@@ -262 +237 @@
                         Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
                         pgmPoolTracDerefGCPhysHint(pPool, pPage,
-                                                   uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
+                                                   PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
                                                    GstPte.u & X86_PTE_PG_MASK,
                                                    iShw);
-                        ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
+                        PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
                     }
                 }
@@ -345 +320 @@
                 const unsigned iShw = off / sizeof(X86PTEPAE);
                 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
-                if (PGM_POOL_IS_PAE_PTE_PRESENT(uShw.pPTPae->a[iShw]))
+                if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
                 {
                     X86PTEPAE GstPte;
@@ -351 +326 @@
                     AssertRC(rc);
 
-                    Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
+                    Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
                     pgmPoolTracDerefGCPhysHint(pPool, pPage,
-                                               uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
+                                               PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
                                                GstPte.u & X86_PTE_PAE_PG_MASK,
                                                iShw);
-                    ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
+                    PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
                 }
 
@@ -366 +341 @@
                     AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
 
-                    if (PGM_POOL_IS_PAE_PTE_PRESENT(uShw.pPTPae->a[iShw2]))
+                    if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw2]))
                     {
                         X86PTEPAE GstPte;
@@ -375 +350 @@
 #   endif
                         AssertRC(rc);
-                        Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
+                        Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
                         pgmPoolTracDerefGCPhysHint(pPool, pPage,
-                                                   uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
+                                                   PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]),
                                                    GstPte.u & X86_PTE_PAE_PG_MASK,
                                                    iShw2);
-                        ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
+                        PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0);
                     }
                 }
@@ -1036 +1011 @@
              * it's fairly safe to assume the guest is reusing the PT.
              */
-            if (PGM_POOL_IS_PAE_PTE_PRESENT(GstPte))
+            if (PGMSHWPTEPAE_IS_P(GstPte))
             {
                 RTHCPHYS HCPhys = -1;
@@ -1103 +1078 @@
         void *pvGst;
         int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
-        pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
+        pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
         PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
         PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
@@ -1374 +1349 @@
  * @param   pGstPT      The guest page table.
  */
-static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
+static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
 {
     unsigned cErrors    = 0;
@@ -1384 +1359 @@
 #ifdef VBOX_STRICT
     for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
-        AssertMsg(!PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u,  pPage->iFirstPresent));
+        AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]),  pPage->iFirstPresent));
 #endif
     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
     {
-        if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
+        if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
         {
             RTHCPHYS HCPhys = NIL_RTHCPHYS;
             int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
             if (    rc != VINF_SUCCESS
-                ||  (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
-            {
-                Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
+                ||  PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
+            {
+                Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
                 LastPTE     = i;
                 LastRc      = rc;
@@ -1411 +1386 @@
                     if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
                     {
-                        PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
+                        PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
 
                         for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
                         {
-                            if (   PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT2->a[j])
-                                && pShwPT2->a[j].n.u1Write
-                                && (pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT)
+                            if (   PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
+                                && PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
                             {
-                                Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
+                                Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
                             }
                         }
@@ -1429 +1403 @@
         }
     }
-    AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, pShwPT->a[LastPTE].u, LastHCPhys));
+    AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
 }
 #  endif /* VBOX_STRICT */
@@ -1445 +1419 @@
  * @param   pfFlush         Flush reused page table (out)
  */
-DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT,
+DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT,
                                                PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
 {
@@ -1452 +1426 @@
 #ifdef VBOX_STRICT
     for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
-        AssertMsg(!PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u,  pPage->iFirstPresent));
+        AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]),  pPage->iFirstPresent));
 #endif
     *pfFlush = false;
@@ -1470 +1444 @@
             }
         }
-        if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
+        if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
         {
             /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
@@ -1478 +1452 @@
                 RTHCPHYS HCPhys = NIL_RTGCPHYS;
                 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
-                AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
+                AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
 #endif
-                uint64_t uHostAttr  = pShwPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
-                bool     fHostRW    = !!(pShwPT->a[i].u & X86_PTE_RW);
+                uint64_t uHostAttr  = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
+                bool     fHostRW    = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
                 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
                 bool     fGuestRW   = !!(pGstPT->a[i].u & X86_PTE_RW);
@@ -1492 +1466 @@
             /* Something was changed, so flush it. */
             Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
-                  i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
-            pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
-            ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
+                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
+            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
+            PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
         }
     }
@@ -1555 +1529 @@
     rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
     bool  fFlush;
-    unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst,
+    unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst,
                                                   (PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0], fAllowRemoval, &fFlush);
     PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
@@ -1631 +1605 @@
 #ifdef VBOX_STRICT
     void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
-    pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
+    pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
     PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
 #endif
@@ -3004 +2978 @@
                         break;
                     default:
+                        /* (shouldn't be here, will assert below) */
                         STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
                         break;
@@ -3054 +3029 @@
         {
             const uint64_t  u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
-            PX86PTPAE       pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
+            PPGMSHWPTPAE    pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
             uint64_t        u64OrMask  = 0;
             uint64_t        u64AndMask = 0;
@@ -3062 +3037 @@
                 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
                 {
-                    case PGM_PAGE_HNDL_PHYS_STATE_NONE:         /** No handler installed. */
-                    case PGM_PAGE_HNDL_PHYS_STATE_DISABLED:     /** Monitoring is temporarily disabled. */
+                    case PGM_PAGE_HNDL_PHYS_STATE_NONE:         /* No handler installed. */
+                    case PGM_PAGE_HNDL_PHYS_STATE_DISABLED:     /* Monitoring is temporarily disabled. */
                         u64OrMask = X86_PTE_RW;
                         u64AndMask = UINT64_MAX;
@@ -3070 +3045 @@
                         break;
 
-                    case PGM_PAGE_HNDL_PHYS_STATE_WRITE:        /** Write access is monitored. */
+                    case PGM_PAGE_HNDL_PHYS_STATE_WRITE:        /* Write access is monitored. */
                         u64OrMask = 0;
                         u64AndMask = ~((uint64_t)X86_PTE_RW);
@@ -3078 +3053 @@
 
                     default:
+                        /* (shouldn't be here, will assert below) */
                         STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
                         break;
@@ -3094 +3070 @@
             }
 
-            if ((pPT->a[iPte].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
+            if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
             {
                 X86PTEPAE Pte;
 
-                Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64\n", iPte, pPT->a[iPte]));
-                Pte.u = (pPT->a[iPte].u & u64AndMask) | u64OrMask;
+                Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64\n", iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
+                Pte.u = (PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & u64AndMask) | u64OrMask;
                 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
                     Pte.n.u1Write = 0;    /* need to disallow writes when dirty bit tracking is still active. */
 
-                ASMAtomicWriteSize(&pPT->a[iPte].u, Pte.u);
+                PGMSHWPTEPAE_ATOMIC_SET(pPT->a[iPte], Pte.u);
                 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
                 return fRet;
@@ -3109 +3085 @@
 #ifdef LOG_ENABLED
             Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
-            Log(("Found %RX64 expected %RX64\n", pPT->a[iPte].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P), u64));
+            Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX), u64));
             for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
-                if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
+                if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
                     Log(("i=%d cFound=%d\n", i, ++cFound));
 #endif
-            AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, pPT->a[iPte].u));
+            AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
             PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
             break;
@@ -3154 +3130 @@
         }
 
-        /* AMD-V nested paging - @todo merge with EPT as we only check the parts that are identical. */
+        /* AMD-V nested paging */ /** @todo merge with EPT as we only check the parts that are identical. */
         case PGMPOOLKIND_PAE_PD_PHYS:
         {
@@ -3277 +3253 @@
  *
  * This is typically called when the host page backing the guest one has been
- * replaced or when the page protection was changed due to an access handler.
+ * replaced or when the page protection was changed due to a guest access
+ * caught by the monitoring.
  *
  * @returns VBox status code.
@@ -3422 +3399 @@
      * This is simple but not quite optimal solution.
      */
-    const uint64_t  u64   = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
-    const uint32_t  u32   = u64;
+    const uint64_t  u64   = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;   /** @todo drop X86_PTE_P here as we always test if present separately, anyway. */
+    const uint32_t  u32   = u64;                                          /** @todo move into the 32BIT_PT_xx case */
     unsigned        cLeft = pPool->cUsedPages;
     unsigned        iPage = pPool->cCurPages;
@@ -3470 +3447 @@
                 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
                 {
-                    unsigned  cPresent = pPage->cPresent;
-                    PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
+                    unsigned        cPresent = pPage->cPresent;
+                    PPGMSHWPTPAE    pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
                     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
-                        if (PGM_POOL_IS_PAE_PTE_PRESENT(pPT->a[i]))
+                        if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
                         {
-                            if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
+                            if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
                             {
                                 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
-                                pPT->a[i].u = 0;
+                                PGMSHWPTEPAE_SET(pPT->a[i], 0); /// @todo why not atomic?
 
                                 /* Update the counter as we're removing references. */
@@ -3498 +3475 @@
                     PEPTPT    pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
                     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
-                        if (PGM_POOL_IS_EPT_PTE_PRESENT(pPT->a[i]))
+                        if (pPT->a[i].n.u1Present)
                         {
                             if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
@@ -4132 +4109 @@
  * @param   pGstPT      The guest page table (just a half one).
  */
-DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
+DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
 {
     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
-        if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
+        if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
         {
             Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
-                  i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
-            pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK, i);
+                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK));
+            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK, i);
             if (!pPage->cPresent)
                 break;
@@ -4154 +4131 @@
  * @param   pGstPT      The guest page table.
  */
-DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
+DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
 {
     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
-        if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
+        if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
         {
             Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
-                  i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
-            pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
+                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
+            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
             if (!pPage->cPresent)
                 break;
@@ -4197 +4174 @@
  * @param   pShwPT      The shadow page table (mapping of the page).
  */
-DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
+DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT)
 {
     RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
-        if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
+        if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
         {
             Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
-                  i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
-            pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys, i);
+                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys));
+            pgmPoolTracDerefGCPhys(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys, i);
             if (!pPage->cPresent)
                 break;
@@ -4223 +4200 @@
     RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
-        if (PGM_POOL_IS_EPT_PTE_PRESENT(pShwPT->a[i]))
+        if (pShwPT->a[i].n.u1Present)
         {
             Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
@@ -4461 +4438 @@
             void *pvGst;
             int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
-            pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
+            pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
             PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
             STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
@@ -4472 +4449 @@
             void *pvGst;
             int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
-            pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
+            pgmPoolTrackDerefPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
             PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
             STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
@@ -4492 +4469 @@
         {
             STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
-            pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
+            pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PPGMSHWPTPAE)pvShw);
             STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
             break;

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -31 +31 @@
 #undef SHW_PD_MASK
 #undef SHW_PTE_PG_MASK
+#undef SHW_PTE_IS_P
+#undef SHW_PTE_IS_RW
+#undef SHW_PTE_IS_US
+#undef SHW_PTE_IS_A
+#undef SHW_PTE_IS_D
+#undef SHW_PTE_IS_P_RW
+#undef SHW_PTE_IS_TRACK_DIRTY
+#undef SHW_PTE_GET_HCPHYS
+#undef SHW_PTE_GET_U
+#undef SHW_PTE_LOG64
+#undef SHW_PTE_SET
+#undef SHW_PTE_ATOMIC_SET
+#undef SHW_PTE_ATOMIC_SET2
+#undef SHW_PTE_SET_RO
+#undef SHW_PTE_SET_RW
 #undef SHW_PT_SHIFT
 #undef SHW_PT_MASK
@@ -40 +55 @@
 
 #if PGM_SHW_TYPE == PGM_TYPE_32BIT
-# define SHWPT                  X86PT
-# define PSHWPT                 PX86PT
-# define SHWPTE                 X86PTE
-# define PSHWPTE                PX86PTE
-# define SHWPD                  X86PD
-# define PSHWPD                 PX86PD
-# define SHWPDE                 X86PDE
-# define PSHWPDE                PX86PDE
-# define SHW_PDE_PG_MASK        X86_PDE_PG_MASK
-# define SHW_PD_SHIFT           X86_PD_SHIFT
-# define SHW_PD_MASK            X86_PD_MASK
-# define SHW_TOTAL_PD_ENTRIES   X86_PG_ENTRIES
-# define SHW_PTE_PG_MASK        X86_PTE_PG_MASK
-# define SHW_PT_SHIFT           X86_PT_SHIFT
-# define SHW_PT_MASK            X86_PT_MASK
-# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PD
+# define SHWPT                          X86PT
+# define PSHWPT                         PX86PT
+# define SHWPTE                         X86PTE
+# define PSHWPTE                        PX86PTE
+# define SHWPD                          X86PD
+# define PSHWPD                         PX86PD
+# define SHWPDE                         X86PDE
+# define PSHWPDE                        PX86PDE
+# define SHW_PDE_PG_MASK                X86_PDE_PG_MASK
+# define SHW_PD_SHIFT                   X86_PD_SHIFT
+# define SHW_PD_MASK                    X86_PD_MASK
+# define SHW_TOTAL_PD_ENTRIES           X86_PG_ENTRIES
+# define SHW_PTE_PG_MASK                X86_PTE_PG_MASK
+# define SHW_PTE_IS_P(Pte)              ( (Pte).n.u1Present )
+# define SHW_PTE_IS_RW(Pte)             ( (Pte).n.u1Write )
+# define SHW_PTE_IS_US(Pte)             ( (Pte).n.u1User )
+# define SHW_PTE_IS_A(Pte)              ( (Pte).n.u1Accessed )
+# define SHW_PTE_IS_D(Pte)              ( (Pte).n.u1Dirty )
+# define SHW_PTE_IS_P_RW(Pte)           ( (Pte).n.u1Present && (Pte).n.u1Write )
+# define SHW_PTE_IS_TRACK_DIRTY(Pte)    ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
+# define SHW_PTE_GET_HCPHYS(Pte)        ( (Pte).u & X86_PTE_PG_MASK )
+# define SHW_PTE_LOG64(Pte)             ( (uint64_t)(Pte).u )
+# define SHW_PTE_GET_U(Pte)             ( (Pte).u )             /**< Use with care. */
+# define SHW_PTE_SET(Pte, uNew)         do { (Pte).u = (uNew); } while (0)
+# define SHW_PTE_ATOMIC_SET(Pte, uNew)  do { ASMAtomicWriteU32(&(Pte).u, (uNew)); } while (0)
+# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU32(&(Pte).u, (Pte2).u); } while (0)
+# define SHW_PTE_SET_RO(Pte)            do { (Pte).n.u1Write = 0; } while (0)
+# define SHW_PTE_SET_RW(Pte)            do { (Pte).n.u1Write = 1; } while (0)
+# define SHW_PT_SHIFT                   X86_PT_SHIFT
+# define SHW_PT_MASK                    X86_PT_MASK
+# define SHW_POOL_ROOT_IDX              PGMPOOL_IDX_PD
 
 #elif PGM_SHW_TYPE == PGM_TYPE_EPT
-# define SHWPT                  EPTPT
-# define PSHWPT                 PEPTPT
-# define SHWPTE                 EPTPTE
-# define PSHWPTE                PEPTPTE
-# define SHWPD                  EPTPD
-# define PSHWPD                 PEPTPD
-# define SHWPDE                 EPTPDE
-# define PSHWPDE                PEPTPDE
-# define SHW_PDE_PG_MASK        EPT_PDE_PG_MASK
-# define SHW_PD_SHIFT           EPT_PD_SHIFT
-# define SHW_PD_MASK            EPT_PD_MASK
-# define SHW_PTE_PG_MASK        EPT_PTE_PG_MASK
-# define SHW_PT_SHIFT           EPT_PT_SHIFT
-# define SHW_PT_MASK            EPT_PT_MASK
-# define SHW_PDPT_SHIFT         EPT_PDPT_SHIFT
-# define SHW_PDPT_MASK          EPT_PDPT_MASK
-# define SHW_PDPE_PG_MASK       EPT_PDPE_PG_MASK
-# define SHW_TOTAL_PD_ENTRIES   (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
-# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_NESTED_ROOT      /* do not use! exception is real mode & protected mode without paging. */
+# define SHWPT                          EPTPT
+# define PSHWPT                         PEPTPT
+# define SHWPTE                         EPTPTE
+# define PSHWPTE                        PEPTPTE
+# define SHWPD                          EPTPD
+# define PSHWPD                         PEPTPD
+# define SHWPDE                         EPTPDE
+# define PSHWPDE                        PEPTPDE
+# define SHW_PDE_PG_MASK                EPT_PDE_PG_MASK
+# define SHW_PD_SHIFT                   EPT_PD_SHIFT
+# define SHW_PD_MASK                    EPT_PD_MASK
+# define SHW_PTE_PG_MASK                EPT_PTE_PG_MASK
+# define SHW_PTE_IS_P(Pte)              ( (Pte).n.u1Present )  /* Approximation, works for us. */
+# define SHW_PTE_IS_RW(Pte)             ( (Pte).n.u1Write )
+# define SHW_PTE_IS_US(Pte)             ( true )
+# define SHW_PTE_IS_A(Pte)              ( true )
+# define SHW_PTE_IS_D(Pte)              ( true )
+# define SHW_PTE_IS_P_RW(Pte)           ( (Pte).n.u1Present && (Pte).n.u1Write )
+# define SHW_PTE_IS_TRACK_DIRTY(Pte)    ( false )
+# define SHW_PTE_GET_HCPHYS(Pte)        ( (Pte).u & X86_PTE_PG_MASK )
+# define SHW_PTE_LOG64(Pte)             ( (Pte).u )
+# define SHW_PTE_GET_U(Pte)             ( (Pte).u )             /**< Use with care. */
+# define SHW_PTE_SET(Pte, uNew)         do { (Pte).u = (uNew); } while (0)
+# define SHW_PTE_ATOMIC_SET(Pte, uNew)  do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
+# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
+# define SHW_PTE_SET_RO(Pte)            do { (Pte).n.u1Write = 0; } while (0)
+# define SHW_PTE_SET_RW(Pte)            do { (Pte).n.u1Write = 1; } while (0)
+# define SHW_PT_SHIFT                   EPT_PT_SHIFT
+# define SHW_PT_MASK                    EPT_PT_MASK
+# define SHW_PDPT_SHIFT                 EPT_PDPT_SHIFT
+# define SHW_PDPT_MASK                  EPT_PDPT_MASK
+# define SHW_PDPE_PG_MASK               EPT_PDPE_PG_MASK
+# define SHW_TOTAL_PD_ENTRIES           (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
+# define SHW_POOL_ROOT_IDX              PGMPOOL_IDX_NESTED_ROOT      /* do not use! exception is real mode & protected mode without paging. */
 
 #else
-# define SHWPT                  X86PTPAE
-# define PSHWPT                 PX86PTPAE
-# define SHWPTE                 X86PTEPAE
-# define PSHWPTE                PX86PTEPAE
-# define SHWPD                  X86PDPAE
-# define PSHWPD                 PX86PDPAE
-# define SHWPDE                 X86PDEPAE
-# define PSHWPDE                PX86PDEPAE
-# define SHW_PDE_PG_MASK        X86_PDE_PAE_PG_MASK
-# define SHW_PD_SHIFT           X86_PD_PAE_SHIFT
-# define SHW_PD_MASK            X86_PD_PAE_MASK
-# define SHW_PTE_PG_MASK        X86_PTE_PAE_PG_MASK
-# define SHW_PT_SHIFT           X86_PT_PAE_SHIFT
-# define SHW_PT_MASK            X86_PT_PAE_MASK
+# define SHWPT                          PGMSHWPTPAE
+# define PSHWPT                         PPGMSHWPTPAE
+# define SHWPTE                         PGMSHWPTEPAE
+# define PSHWPTE                        PPGMSHWPTEPAE
+# define SHWPD                          X86PDPAE
+# define PSHWPD                         PX86PDPAE
+# define SHWPDE                         X86PDEPAE
+# define PSHWPDE                        PX86PDEPAE
+# define SHW_PDE_PG_MASK                X86_PDE_PAE_PG_MASK
+# define SHW_PD_SHIFT                   X86_PD_PAE_SHIFT
+# define SHW_PD_MASK                    X86_PD_PAE_MASK
+# define SHW_PTE_PG_MASK                X86_PTE_PAE_PG_MASK
+# define SHW_PTE_IS_P(Pte)              PGMSHWPTEPAE_IS_P(Pte)
+# define SHW_PTE_IS_RW(Pte)             PGMSHWPTEPAE_IS_RW(Pte)
+# define SHW_PTE_IS_US(Pte)             PGMSHWPTEPAE_IS_US(Pte)
+# define SHW_PTE_IS_A(Pte)              PGMSHWPTEPAE_IS_A(Pte)
+# define SHW_PTE_IS_D(Pte)              PGMSHWPTEPAE_IS_D(Pte)
+# define SHW_PTE_IS_P_RW(Pte)           PGMSHWPTEPAE_IS_P_RW(Pte)
+# define SHW_PTE_IS_TRACK_DIRTY(Pte)    PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)
+# define SHW_PTE_GET_HCPHYS(Pte)        PGMSHWPTEPAE_GET_HCPHYS(Pte)
+# define SHW_PTE_LOG64(Pte)             PGMSHWPTEPAE_GET_LOG(Pte)
+# define SHW_PTE_GET_U(Pte)             PGMSHWPTEPAE_GET_U(Pte)     /**< Use with care. */
+# define SHW_PTE_SET(Pte, uNew)         PGMSHWPTEPAE_SET(Pte, uNew)
+# define SHW_PTE_ATOMIC_SET(Pte, uNew)  PGMSHWPTEPAE_ATOMIC_SET(Pte, uNew)
+# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)
+# define SHW_PTE_SET_RO(Pte)            PGMSHWPTEPAE_SET_RO(Pte)
+# define SHW_PTE_SET_RW(Pte)            PGMSHWPTEPAE_SET_RW(Pte)
+# define SHW_PT_SHIFT                   X86_PT_PAE_SHIFT
+# define SHW_PT_MASK                    X86_PT_PAE_MASK
 
 # if PGM_SHW_TYPE == PGM_TYPE_AMD64
-#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
-#  define SHW_PDPT_MASK         X86_PDPT_MASK_AMD64
-#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
-#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
-#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_AMD64_CR3
+#  define SHW_PDPT_SHIFT                X86_PDPT_SHIFT
+#  define SHW_PDPT_MASK                 X86_PDPT_MASK_AMD64
+#  define SHW_PDPE_PG_MASK              X86_PDPE_PG_MASK
+#  define SHW_TOTAL_PD_ENTRIES          (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
+#  define SHW_POOL_ROOT_IDX             PGMPOOL_IDX_AMD64_CR3
 
 # else /* 32 bits PAE mode */
-#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
-#  define SHW_PDPT_MASK         X86_PDPT_MASK_PAE
-#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
-#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
-#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PDPT
+#  define SHW_PDPT_SHIFT                X86_PDPT_SHIFT
+#  define SHW_PDPT_MASK                 X86_PDPT_MASK_PAE
+#  define SHW_PDPE_PG_MASK              X86_PDPE_PG_MASK
+#  define SHW_TOTAL_PD_ENTRIES          (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
+#  define SHW_POOL_ROOT_IDX             PGMPOOL_IDX_PDPT
 
 # endif
@@ -254 +314 @@
     const unsigned  iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
     SHWPTE          Pte = pPT->a[iPt];
-    if (!Pte.n.u1Present)
+    if (!SHW_PTE_IS_P(Pte))
         return VERR_PAGE_NOT_PRESENT;
 
@@ -264 +324 @@
     if (pfFlags)
     {
-        *pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
+        *pfFlags = (SHW_PTE_GET_U(Pte) & ~SHW_PTE_PG_MASK)
                  & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
 # if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) /** @todo why do we have to check the guest state here? */
         /* The NX bit is determined by a bitwise OR between the PT and PD */
-        if (((Pte.u | Pde.u) & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
+        if (((SHW_PTE_GET_U(Pte) | Pde.u) & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
             *pfFlags |= X86_PTE_PAE_NX;
 # endif
@@ -274 +334 @@
 
     if (pHCPhys)
-        *pHCPhys = Pte.u & SHW_PTE_PG_MASK;
+        *pHCPhys = SHW_PTE_GET_HCPHYS(Pte);
 
     return VINF_SUCCESS;
@@ -375 +435 @@
         while (iPTE < RT_ELEMENTS(pPT->a))
         {
-            if (pPT->a[iPTE].n.u1Present)
+            if (SHW_PTE_IS_P(pPT->a[iPTE]))
             {
                 SHWPTE const    OrgPte = pPT->a[iPTE];
                 SHWPTE          NewPte;
 
-                NewPte.u = (OrgPte.u & (fMask | SHW_PTE_PG_MASK)) | (fFlags & ~SHW_PTE_PG_MASK);
-                Assert(NewPte.n.u1Present);
-                if (!NewPte.n.u1Present)
+                SHW_PTE_SET(NewPte, (SHW_PTE_GET_U(OrgPte) & (fMask | SHW_PTE_PG_MASK)) | (fFlags & ~SHW_PTE_PG_MASK));
+                if (!SHW_PTE_IS_P(NewPte))
                 {
                     /** @todo Some CSAM code path might end up here and upset
@@ -388 +447 @@
                     AssertFailed();
                 }
-                else if (   NewPte.n.u1Write
-                         && !OrgPte.n.u1Write
+                else if (   SHW_PTE_IS_RW(NewPte)
+                         && !SHW_PTE_IS_RW(OrgPte)
                          && !(fOpFlags & PGM_MK_PG_IS_MMIO2) )
                 {
@@ -414 +473 @@
                 }
 
-                ASMAtomicWriteSize(&pPT->a[iPTE], NewPte.u);
+                SHW_PTE_ATOMIC_SET2(pPT->a[iPTE], NewPte);
 # if PGM_SHW_TYPE == PGM_TYPE_EPT
                 HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);

trunk/src/VBox/VMM/VMMGC/PGMGCShw.h

@@ -50 +50 @@
 # define SHW_PT_MASK            X86_PT_MASK
 #else
-# define SHWPT                  X86PTPAE
-# define PSHWPT                 PX86PTPAE
-# define SHWPTE                 X86PTEPAE
-# define PSHWPTE                PX86PTEPAE
+# define SHWPT                  PGMSHWPTPAE
+# define PSHWPT                 PPGMSHWPTPAE
+# define SHWPTE                 PGMSHWPTEPAE
+# define PSHWPTE                PPGMSHWPTEPAE
 # define SHWPD                  X86PDPAE
 # define PSHWPD                 PX86PDPAE

trunk/src/VBox/VMM/VMMRZ/PGMRZDynMap.cpp

@@ -1291 +1291 @@
             pThis->paPages[iPage].uPte.pLegacy = &pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage];
         else
-            pThis->paPages[iPage].uPte.pPae    = &pVM->pgm.s.paDynPageMapPaePTEsGC[iPage];
+            pThis->paPages[iPage].uPte.pPae    = (PX86PTEPAE)&pVM->pgm.s.paDynPageMapPaePTEsGC[iPage];
     }