Changeset 32000 in vbox for trunk/src/VBox

Timestamp:

Aug 26, 2010 2:08:55 PM (14 years ago)

Author:

vboxsync

Message:

x86.h,*: Eliminated X86_PML4E_PG_MASK and renamed X86_PML4E_PG_MASK_FULL to X86_PML4E_PG_MASK.

Location:

trunk/src/VBox

Files:

• Debugger/DBGCEmulateCodeView.cpp (modified) (2 diffs)
• VMM/PGMDbg.cpp (modified) (4 diffs)
• VMM/PGMInline.h (modified) (2 diffs)
• VMM/VMMAll/PGMAll.cpp (modified) (4 diffs)
• VMM/VMMAll/PGMAllBth.h (modified) (1 diff)
• VMM/VMMAll/PGMAllGst.h (modified) (1 diff)
• VMM/VMMAll/PGMAllPool.cpp (modified) (3 diffs)
• VMM/VMMAll/PGMAllShw.h (modified) (2 diffs)
• VMM/VMMRZ/PGMRZDynMap.cpp (modified) (1 diff)

trunk/src/VBox/Debugger/DBGCEmulateCodeView.cpp

@@ -2731 +2731 @@
                 return DBGCCmdHlpPrintf(pCmdHlp, "Page directory pointer table is not present for %Dv.\n", &VarGCPtr);
 
-            VarCur.u.u64Number = Pml4e.u & X86_PML4E_PG_MASK_FULL;
+            VarCur.u.u64Number = Pml4e.u & X86_PML4E_PG_MASK;
             Assert(fPAE);
         }
@@ -3102 +3102 @@
                 return DBGCCmdHlpPrintf(pCmdHlp, "Page directory pointer table is not present for %Dv.\n", &VarGCPtr);
 
-            VarCur.u.u64Number = Pml4e.u & X86_PML4E_PG_MASK_FULL;
+            VarCur.u.u64Number = Pml4e.u & X86_PML4E_PG_MASK;
             Assert(fPAE);
         }

trunk/src/VBox/VMM/PGMDbg.cpp

@@ -1376 +1376 @@
                                     Pml4e.u & PGM_PLXFLAGS_PERMANENT   ? 'p' : '-',
                                     Pml4e.u & RT_BIT(11)               ? '1' : '0',
-                                    Pml4e.u & X86_PML4E_PG_MASK_FULL);
+                                    Pml4e.u & X86_PML4E_PG_MASK);
             if (pState->fDumpPageInfo)
-                pgmR3DumpHierarchyShwTablePageInfo(pState, Pml4e.u & X86_PML4E_PG_MASK_FULL);
+                pgmR3DumpHierarchyShwTablePageInfo(pState, Pml4e.u & X86_PML4E_PG_MASK);
             if ((Pml4e.u >> 52) & 0x7ff)
                 pState->pHlp->pfnPrintf(pState->pHlp, " 62:52=%03llx!", (Pml4e.u >> 52) & 0x7ff);
@@ -1385 +1385 @@
             if (cMaxDepth)
             {
-                int rc2 = pgmR3DumpHierarchyShwPaePDPT(pState, Pml4e.u & X86_PML4E_PG_MASK_FULL, cMaxDepth);
+                int rc2 = pgmR3DumpHierarchyShwPaePDPT(pState, Pml4e.u & X86_PML4E_PG_MASK, cMaxDepth);
                 if (rc2 < rc && RT_SUCCESS(rc))
                     rc = rc2;
@@ -2049 +2049 @@
                                     Pml4e.u & RT_BIT_64(10) ? '1' : '0',
                                     Pml4e.u & RT_BIT_64(11) ? '1' : '0',
-                                    Pml4e.u & X86_PML4E_PG_MASK_FULL);
+                                    Pml4e.u & X86_PML4E_PG_MASK);
             if (pState->fDumpPageInfo)
-                pgmR3DumpHierarchyGstPageInfo(pState, Pml4e.u & X86_PML4E_PG_MASK_FULL, _4K);
+                pgmR3DumpHierarchyGstPageInfo(pState, Pml4e.u & X86_PML4E_PG_MASK, _4K);
             pgmR3DumpHierarchyGstCheckReservedHighBits(pState, Pml4e.u);
             pState->pHlp->pfnPrintf(pState->pHlp, "\n");
@@ -2057 +2057 @@
             if (cMaxDepth)
             {
-                int rc2 = pgmR3DumpHierarchyGstPaePDPT(pState, Pml4e.u & X86_PML4E_PG_MASK_FULL, cMaxDepth);
+                int rc2 = pgmR3DumpHierarchyGstPaePDPT(pState, Pml4e.u & X86_PML4E_PG_MASK, cMaxDepth);
                 if (rc2 < rc && RT_SUCCESS(rc))
                     rc = rc2;

trunk/src/VBox/VMM/PGMInline.h

@@ -924 +924 @@
     {
         PCX86PDPT   pPdptTemp;
-        int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK_FULL, &pPdptTemp);
+        int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
         if (RT_SUCCESS(rc))
         {
@@ -974 +974 @@
     /* The PDPE. */
     PCX86PDPT       pPdptTemp;
-    int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pPml4e->u & X86_PML4E_PG_MASK_FULL, &pPdptTemp);
+    int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
     if (RT_FAILURE(rc))
     {

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -1074 +1074 @@
     /* Allocate page directory pointer table if not present. */
     if (    !pPml4e->n.u1Present
-        &&  !(pPml4e->u & X86_PML4E_PG_MASK_FULL))
+        &&  !(pPml4e->u & X86_PML4E_PG_MASK))
     {
         RTGCPTR64   GCPml4;
@@ -1089 +1089 @@
         else
         {
-            GCPml4  = uGstPml4e & X86_PML4E_PG_MASK_FULL;
+            GCPml4  = uGstPml4e & X86_PML4E_PG_MASK;
             enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
         }
@@ -1099 +1099 @@
     else
     {
-        pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK_FULL);
+        pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
         AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
 
@@ -1177 +1177 @@
     PVM             pVM      = pVCpu->CTX_SUFF(pVM);
     PPGMPOOL        pPool    = pVM->pgm.s.CTX_SUFF(pPool);
-    PPGMPOOLPAGE    pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK_FULL);
+    PPGMPOOLPAGE    pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
     AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
 

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -3669 +3669 @@
         }
 
-        pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK_FULL);
-        GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
+        pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
+        GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
 
         if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -115 +115 @@
          * The PDPE.
          */
-        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & X86_PML4E_PG_MASK_FULL, &pWalk->pPdpt);
+        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pWalk->pPdpt);
         if (RT_FAILURE(rc))
             return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -662 +662 @@
                 {
                     LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
-                    pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK_FULL, pPage->idx, iShw);
+                    pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
                     ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
                 }
@@ -673 +673 @@
                     {
                         LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
-                        pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK_FULL, pPage->idx, iShw2);
+                        pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
                         ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
                     }
@@ -4348 +4348 @@
                 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
             else
-                AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK_FULL));
+                AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
             /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
         }

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -217 +217 @@
     /* PDPT */
     PX86PDPT        pPDPT;
-    int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK_FULL, &pPDPT);
+    int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
     if (RT_FAILURE(rc))
         return rc;
@@ -383 +383 @@
         /* PDPT */
         PX86PDPT        pPDPT;
-        rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK_FULL, &pPDPT);
+        rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
         if (RT_FAILURE(rc))
             return rc;

trunk/src/VBox/VMM/VMMRZ/PGMRZDynMap.cpp

@@ -756 +756 @@
             pPgLvl->a[0].fResMask  = X86_PML4E_P | X86_PML4E_RW;
 
-            pPgLvl->a[1].fPhysMask = X86_PML4E_PG_MASK_FULL;
+            pPgLvl->a[1].fPhysMask = X86_PML4E_PG_MASK;
             pPgLvl->a[1].fPtrShift = X86_PDPT_SHIFT;
             pPgLvl->a[1].fPtrMask  = X86_PDPT_MASK_AMD64;