- Timestamp:
- Aug 27, 2010 10:14:39 AM (14 years ago)
- Location:
- trunk/src/VBox
- Files:
-
- 25 edited
-
Debugger/DBGCEmulateCodeView.cpp (modified) (3 diffs)
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HostDrivers/Support/SUPLib.cpp (modified) (4 diffs)
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VMM/MM.cpp (modified) (2 diffs)
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VMM/MMPagePool.cpp (modified) (1 diff)
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VMM/PGMDbg.cpp (modified) (3 diffs)
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VMM/PGMGstDefs.h (modified) (4 diffs)
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VMM/PGMInline.h (modified) (2 diffs)
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VMM/PGMInternal.h (modified) (2 diffs)
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VMM/PGMMap.cpp (modified) (1 diff)
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VMM/PGMPool.cpp (modified) (1 diff)
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VMM/PGMShw.h (modified) (1 diff)
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VMM/VMMAll/MMAllPagePool.cpp (modified) (1 diff)
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VMM/VMMAll/PGMAll.cpp (modified) (2 diffs)
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VMM/VMMAll/PGMAllBth.h (modified) (3 diffs)
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VMM/VMMAll/PGMAllGst.h (modified) (1 diff)
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VMM/VMMAll/PGMAllHandler.cpp (modified) (11 diffs)
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VMM/VMMAll/PGMAllMap.cpp (modified) (4 diffs)
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VMM/VMMAll/PGMAllPhys.cpp (modified) (2 diffs)
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VMM/VMMAll/PGMAllPool.cpp (modified) (15 diffs)
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VMM/VMMAll/PGMAllShw.h (modified) (1 diff)
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VMM/VMMGC/PGMGCGst.h (modified) (1 diff)
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VMM/VMMGC/PGMGCShw.h (modified) (1 diff)
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VMM/VMMR0/PGMR0.cpp (modified) (2 diffs)
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VMM/VMMRZ/PGMRZDynMap.cpp (modified) (4 diffs)
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VMM/testcase/tstCompiler.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Debugger/DBGCEmulateCodeView.cpp
r32034 r32036 2722 2722 /* Page Map Level 4 Lookup. */ 2723 2723 /* Check if it's a valid address first? */ 2724 VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK _FULL;2724 VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK; 2725 2725 VarCur.u.u64Number += (((uint64_t)VarGCPtr.u.GCFlat >> X86_PML4_SHIFT) & X86_PML4_MASK) * sizeof(X86PML4E); 2726 2726 X86PML4E Pml4e; … … 3093 3093 /* Page Map Level 4 Lookup. */ 3094 3094 /* Check if it's a valid address first? */ 3095 VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK _FULL;3095 VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK; 3096 3096 VarCur.u.u64Number += (((uint64_t)VarGCPtr.u.GCFlat >> X86_PML4_SHIFT) & X86_PML4_MASK) * sizeof(X86PML4E); 3097 3097 X86PML4E Pml4e; … … 3189 3189 : "%08llx 4kb phys=%08llx %s %s %s %s %s avl=%02x %s %s %s %s %s", 3190 3190 Pte.u, 3191 Pte.u & X86_PTE_PAE_PG_MASK _FULL,3191 Pte.u & X86_PTE_PAE_PG_MASK, 3192 3192 Pte.n.u1Present ? "p " : "np", 3193 3193 Pte.n.u1Write ? "w" : "r", -
trunk/src/VBox/HostDrivers/Support/SUPLib.cpp
r32035 r32036 926 926 paPages[iPage].uReserved = 0; 927 927 paPages[iPage].Phys = pReq->u.Out.aPages[iPage]; 928 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK _FULL));928 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK)); 929 929 } 930 930 } … … 1021 1021 paPages[iPage].uReserved = 0; 1022 1022 paPages[iPage].Phys = (iPage + 4321) << PAGE_SHIFT; 1023 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK _FULL));1023 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK)); 1024 1024 } 1025 1025 return VINF_SUCCESS; … … 1065 1065 paPages[iPage].uReserved = 0; 1066 1066 paPages[iPage].Phys = pReq->u.Out.aPages[iPage]; 1067 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK _FULL));1067 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK)); 1068 1068 } 1069 1069 #ifdef RT_OS_DARWIN /* HACK ALERT! */ … … 1352 1352 paPages[iPage].uReserved = 0; 1353 1353 paPages[iPage].Phys = pReq->u.Out.aPages[iPage]; 1354 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK _FULL));1354 Assert(!(paPages[iPage].Phys & ~X86_PTE_PAE_PG_MASK)); 1355 1355 Assert(paPages[iPage].Phys <= UINT32_C(0xfffff000)); 1356 1356 } -
trunk/src/VBox/VMM/MM.cpp
r32035 r32036 319 319 else 320 320 AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc), rc); 321 AssertLogRelMsg(!(cbRam & ~X86_PTE_PAE_PG_MASK _FULL), ("%RGp X86_PTE_PAE_PG_MASK_FULL=%RX64\n", cbRam, X86_PTE_PAE_PG_MASK_FULL));321 AssertLogRelMsg(!(cbRam & ~X86_PTE_PAE_PG_MASK), ("%RGp X86_PTE_PAE_PG_MASK=%RX64\n", cbRam, X86_PTE_PAE_PG_MASK)); 322 322 AssertLogRelMsgReturn(cbRam <= GMM_GCPHYS_LAST, ("cbRam=%RGp GMM_GCPHYS_LAST=%RX64\n", cbRam, GMM_GCPHYS_LAST), VERR_OUT_OF_RANGE); 323 cbRam &= X86_PTE_PAE_PG_MASK _FULL;323 cbRam &= X86_PTE_PAE_PG_MASK; 324 324 pVM->mm.s.cbRamBase = cbRam; 325 325 … … 740 740 */ 741 741 uint32_t off = HCPhys & PAGE_OFFSET_MASK; 742 HCPhys &= X86_PTE_PAE_PG_MASK _FULL;742 HCPhys &= X86_PTE_PAE_PG_MASK; 743 743 PMMLOOKUPHYPER pCur = (PMMLOOKUPHYPER)((uint8_t *)pVM->mm.s.CTX_SUFF(pHyperHeap) + pVM->mm.s.offLookupHyper); 744 744 for (;;) -
trunk/src/VBox/VMM/MMPagePool.cpp
r32035 r32036 502 502 AssertRelease(pVM->mm.s.pvDummyPage); 503 503 pVM->mm.s.HCPhysDummyPage = mmPagePoolPtr2Phys(pVM->mm.s.pPagePoolR3, pVM->mm.s.pvDummyPage); 504 AssertRelease(!(pVM->mm.s.HCPhysDummyPage & ~X86_PTE_PAE_PG_MASK _FULL));504 AssertRelease(!(pVM->mm.s.HCPhysDummyPage & ~X86_PTE_PAE_PG_MASK)); 505 505 } 506 506 return pVM->mm.s.pvDummyPage; -
trunk/src/VBox/VMM/PGMDbg.cpp
r32034 r32036 156 156 return VERR_INVALID_POINTER; 157 157 unsigned off = HCPhys & PAGE_OFFSET_MASK; 158 HCPhys &= X86_PTE_PAE_PG_MASK _FULL;158 HCPhys &= X86_PTE_PAE_PG_MASK; 159 159 if (HCPhys == 0) 160 160 return VERR_INVALID_POINTER; … … 1104 1104 Pte.u & RT_BIT(10) ? '1' : '0', 1105 1105 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-', 1106 Pte.u & X86_PTE_PAE_PG_MASK _FULL);1106 Pte.u & X86_PTE_PAE_PG_MASK); 1107 1107 if (pState->fDumpPageInfo) 1108 pgmR3DumpHierarchyShwGuestPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK _FULL, _4K);1108 pgmR3DumpHierarchyShwGuestPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK, _4K); 1109 1109 if ((Pte.u >> 52) & 0x7ff) 1110 1110 pState->pHlp->pfnPrintf(pState->pHlp, " 62:52=%03llx%s", (Pte.u >> 52) & 0x7ff, pState->fLme ? "" : "!"); … … 1785 1785 Pte.u & RT_BIT(10) ? '1' : '0', 1786 1786 Pte.u & RT_BIT(11) ? '1' : '0', 1787 Pte.u & X86_PTE_PAE_PG_MASK _FULL);1787 Pte.u & X86_PTE_PAE_PG_MASK); 1788 1788 if (pState->fDumpPageInfo) 1789 pgmR3DumpHierarchyGstPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK _FULL, _4K);1789 pgmR3DumpHierarchyGstPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK, _4K); 1790 1790 pgmR3DumpHierarchyGstCheckReservedHighBits(pState, Pte.u); 1791 1791 pState->pHlp->pfnPrintf(pState->pHlp, "\n"); -
trunk/src/VBox/VMM/PGMGstDefs.h
r32034 r32036 75 75 # define GSTPDE X86PDEPAE 76 76 # define PGSTPDE PX86PDEPAE 77 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL77 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK 78 78 # define GST_IS_NX_ACTIVE(pVCpu) (true && This_should_perhaps_not_be_used_in_this_context) 79 79 # define BTH_IS_NP_ACTIVE(pVM) (true) … … 98 98 # define GSTPDE X86PDEPAE 99 99 # define PGSTPDE PX86PDEPAE 100 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL100 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK 101 101 # endif 102 102 # define GST_IS_NX_ACTIVE(pVCpu) (pgmGstIsNoExecuteActive(pVCpu)) … … 197 197 # define GST_PDPT_SHIFT X86_PDPT_SHIFT 198 198 # define GST_PDPT_MASK X86_PDPT_MASK_PAE 199 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL199 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK 200 200 # define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK 201 201 # define GST_IS_PTE_VALID(pVCpu, Pte) (!( (Pte).u & (pVCpu)->pgm.s.fGstPaeMbzPteMask )) … … 214 214 # define GST_PDPE_PG_MASK X86_PDPE_PG_MASK 215 215 # define GST_PDPT_MASK X86_PDPT_MASK_AMD64 216 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL216 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK 217 217 # define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK 218 218 # define GST_IS_PTE_VALID(pVCpu, Pte) (!( (Pte).u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask )) -
trunk/src/VBox/VMM/PGMInline.h
r32009 r32036 521 521 int rc; 522 522 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)]; 523 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK _FULL))523 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK)) 524 524 { 525 525 STAM_COUNTER_INC(&pPGM->CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageMapTlbHits)); … … 551 551 int rc; 552 552 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)]; 553 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK _FULL))553 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK)) 554 554 { 555 555 STAM_COUNTER_INC(&pPGM->CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageMapTlbHits)); -
trunk/src/VBox/VMM/PGMInternal.h
r32035 r32036 442 442 # define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) ) 443 443 # define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful ) 444 # define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK _FULL)444 # define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK ) 445 445 # define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */ 446 446 # define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0) … … 472 472 # define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) ) 473 473 # define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u ) 474 # define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK _FULL)474 # define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK ) 475 475 # define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */ 476 476 # define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0) -
trunk/src/VBox/VMM/PGMMap.cpp
r32035 r32036 782 782 cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK; 783 783 cbPages = RT_ALIGN(cbPages, PAGE_SIZE); 784 HCPhys &= X86_PTE_PAE_PG_MASK _FULL;784 HCPhys &= X86_PTE_PAE_PG_MASK; 785 785 Addr &= PAGE_BASE_MASK; 786 786 /* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */ -
trunk/src/VBox/VMM/PGMPool.cpp
r31996 r32036 931 931 { 932 932 RTHCPHYS HCPhys = NIL_RTHCPHYS; 933 rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[j].u & X86_PTE_PAE_PG_MASK _FULL, &HCPhys);933 rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[j].u & X86_PTE_PAE_PG_MASK, &HCPhys); 934 934 if ( rc != VINF_SUCCESS 935 935 || PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[j]) != HCPhys) -
trunk/src/VBox/VMM/PGMShw.h
r32035 r32036 90 90 # define SHW_PD_SHIFT X86_PD_PAE_SHIFT 91 91 # define SHW_PD_MASK X86_PD_PAE_MASK 92 # define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL92 # define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK 93 93 # define SHW_PT_SHIFT X86_PT_PAE_SHIFT 94 94 # define SHW_PT_MASK X86_PT_PAE_MASK -
trunk/src/VBox/VMM/VMMAll/MMAllPagePool.cpp
r32035 r32036 62 62 * Lookup the virtual address. 63 63 */ 64 PMMPPLOOKUPHCPHYS pLookup = (PMMPPLOOKUPHCPHYS)RTAvlHCPhysGet(&pPool->pLookupPhys, HCPhys & X86_PTE_PAE_PG_MASK _FULL);64 PMMPPLOOKUPHCPHYS pLookup = (PMMPPLOOKUPHCPHYS)RTAvlHCPhysGet(&pPool->pLookupPhys, HCPhys & X86_PTE_PAE_PG_MASK); 65 65 if (pLookup) 66 66 { -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r32009 r32036 854 854 DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags) 855 855 { 856 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK _FULL), ("fFlags=%#llx\n", fFlags));856 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags)); 857 857 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT))); 858 858 … … 1406 1406 * Validate input. 1407 1407 */ 1408 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK _FULL), ("fFlags=%#llx\n", fFlags));1408 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags)); 1409 1409 Assert(cb); 1410 1410 -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r32035 r32036 353 353 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) ) 354 354 { 355 Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK _FULL) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK_FULL));355 Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK)); 356 356 # ifdef IN_RC 357 357 STAM_PROFILE_START(&pCur->Stat, h); … … 4217 4217 continue; 4218 4218 4219 fIgnoreFlags = X86_PTE_PAE_PG_MASK _FULL| X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX;4219 fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX; 4220 4220 4221 4221 /* match the physical addresses */ … … 4233 4233 } 4234 4234 } 4235 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK _FULL))4235 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK)) 4236 4236 { 4237 4237 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n", -
trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
r32009 r32036 353 353 { 354 354 GSTPTE Pte = Walk.pPt->a[iPTE]; 355 Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK _FULL))355 Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK)) 356 356 | (fFlags & ~GST_PTE_PG_MASK); 357 357 Walk.pPt->a[iPTE] = Pte; -
trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp
r31996 r32036 145 145 pNew->Core.KeyLast = GCPhysLast; 146 146 pNew->enmType = enmType; 147 pNew->cPages = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK _FULL) + PAGE_SIZE) >> PAGE_SHIFT;147 pNew->cPages = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT; 148 148 pNew->pfnHandlerR3 = pfnHandlerR3; 149 149 pNew->pvUserR3 = pvUserR3; … … 307 307 && PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE) 308 308 { 309 RTGCPHYS GCPhys = (GCPhysStart + (PAGE_SIZE - 1)) & X86_PTE_PAE_PG_MASK _FULL;309 RTGCPHYS GCPhys = (GCPhysStart + (PAGE_SIZE - 1)) & X86_PTE_PAE_PG_MASK; 310 310 if ( GCPhys > GCPhysLast 311 311 || GCPhys < GCPhysStart) … … 314 314 } 315 315 else 316 GCPhysStart &= X86_PTE_PAE_PG_MASK _FULL;316 GCPhysStart &= X86_PTE_PAE_PG_MASK; 317 317 Assert(!pPage || PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO); /* these are page aligned atm! */ 318 318 } … … 324 324 && PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE) 325 325 { 326 RTGCPHYS GCPhys = (GCPhysLast & X86_PTE_PAE_PG_MASK _FULL) - 1;326 RTGCPHYS GCPhys = (GCPhysLast & X86_PTE_PAE_PG_MASK) - 1; 327 327 if ( GCPhys < GCPhysStart 328 328 || GCPhys > GCPhysLast) … … 536 536 pCur->Core.Key = GCPhys; 537 537 pCur->Core.KeyLast = GCPhysLast; 538 pCur->cPages = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK _FULL) + 1) >> PAGE_SHIFT;538 pCur->cPages = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK) + 1) >> PAGE_SHIFT; 539 539 540 540 if (RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pCur->Core)) … … 684 684 *pNew = *pCur; 685 685 pNew->Core.Key = GCPhysSplit; 686 pNew->cPages = (pNew->Core.KeyLast - (pNew->Core.Key & X86_PTE_PAE_PG_MASK _FULL) + PAGE_SIZE) >> PAGE_SHIFT;686 pNew->cPages = (pNew->Core.KeyLast - (pNew->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT; 687 687 688 688 pCur->Core.KeyLast = GCPhysSplit - 1; 689 pCur->cPages = (pCur->Core.KeyLast - (pCur->Core.Key & X86_PTE_PAE_PG_MASK _FULL) + PAGE_SIZE) >> PAGE_SHIFT;689 pCur->cPages = (pCur->Core.KeyLast - (pCur->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT; 690 690 691 691 if (RT_LIKELY(RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pNew->Core))) … … 750 750 { 751 751 pCur1->Core.KeyLast = pCur2->Core.KeyLast; 752 pCur1->cPages = (pCur1->Core.KeyLast - (pCur1->Core.Key & X86_PTE_PAE_PG_MASK _FULL) + PAGE_SIZE) >> PAGE_SHIFT;752 pCur1->cPages = (pCur1->Core.KeyLast - (pCur1->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT; 753 753 LogFlow(("PGMHandlerPhysicalJoin: %RGp-%RGp %RGp-%RGp\n", 754 754 pCur1->Core.Key, pCur1->Core.KeyLast, pCur2->Core.Key, pCur2->Core.KeyLast)); … … 1481 1481 for (unsigned iPage = 0; iPage < pCur->cPages; iPage++) 1482 1482 { 1483 if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK _FULL) == pState->GCPhys)1483 if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == pState->GCPhys) 1484 1484 { 1485 1485 unsigned uState = pgmHandlerVirtualCalcState(pCur); … … 1574 1574 1575 1575 AssertRCReturn(rc, 0); 1576 if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK _FULL) != GCPhysGst)1576 if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) != GCPhysGst) 1577 1577 { 1578 1578 AssertMsgFailed(("virt handler phys out of sync. %RGp GCPhysGst=%RGp iPage=%#x %RGv %s\n", … … 1713 1713 GCPhysKey, true /* above-or-equal */); 1714 1714 if ( !pPhys2Virt 1715 || (pPhys2Virt->Core.Key & X86_PTE_PAE_PG_MASK _FULL) != State.GCPhys)1715 || (pPhys2Virt->Core.Key & X86_PTE_PAE_PG_MASK) != State.GCPhys) 1716 1716 break; 1717 1717 … … 1732 1732 1733 1733 /* done? */ 1734 if ((GCPhysKey & X86_PTE_PAE_PG_MASK _FULL) != State.GCPhys)1734 if ((GCPhysKey & X86_PTE_PAE_PG_MASK) != State.GCPhys) 1735 1735 break; 1736 1736 } -
trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp
r32035 r32036 75 75 */ 76 76 X86PTEPAE Pte; 77 Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK _FULL);77 Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK); 78 78 79 79 /* … … 144 144 * Validate input. 145 145 */ 146 AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK _FULL| X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));146 AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags)); 147 147 Assert(cb); 148 148 … … 185 185 PGMSHWPTEPAE_SET(*pPtePae, 186 186 ( PGMSHWPTEPAE_GET_U(*pPtePae) 187 & (fMask | X86_PTE_PAE_PG_MASK _FULL))188 | (fFlags & ~(X86_PTE_PAE_PG_MASK _FULL| X86_PTE_PAE_MBZ_MASK_NX)));187 & (fMask | X86_PTE_PAE_PG_MASK)) 188 | (fFlags & ~(X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX))); 189 189 190 190 /* invalidate tls */ … … 243 243 { 244 244 if (pfFlags) 245 *pfFlags = PGMSHWPTEPAE_GET_U(*pPtePae) & ~X86_PTE_PAE_PG_MASK _FULL;245 *pfFlags = PGMSHWPTEPAE_GET_U(*pPtePae) & ~X86_PTE_PAE_PG_MASK; 246 246 if (pHCPhys) 247 247 *pHCPhys = PGMSHWPTEPAE_GET_HCPHYS(*pPtePae); -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r32035 r32036 421 421 AssertMsg(iHandyPage < RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d\n", iHandyPage)); 422 422 Assert(pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys != NIL_RTHCPHYS); 423 Assert(!(pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK _FULL));423 Assert(!(pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK)); 424 424 Assert(pVM->pgm.s.aHandyPages[iHandyPage].idPage != NIL_GMM_PAGEID); 425 425 Assert(pVM->pgm.s.aHandyPages[iHandyPage].idSharedPage == NIL_GMM_PAGEID); … … 1078 1078 if ( PGM_PAGE_GET_TYPE(pPage) < PGMPAGETYPE_ROM_SHADOW 1079 1079 || PGM_PAGE_GET_TYPE(pPage) > PGMPAGETYPE_ROM) 1080 pTlbe->GCPhys = GCPhys & X86_PTE_PAE_PG_MASK _FULL;1080 pTlbe->GCPhys = GCPhys & X86_PTE_PAE_PG_MASK; 1081 1081 else 1082 1082 pTlbe->GCPhys = NIL_RTGCPHYS; /* ROM: Problematic because of the two pages. :-/ */ -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r32035 r32036 210 210 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte)); 211 211 AssertRC(rc); 212 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK _FULL, GstPte.u & X86_PTE_PG_MASK));212 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK)); 213 213 pgmPoolTracDerefGCPhysHint(pPool, pPage, 214 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK _FULL,214 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, 215 215 GstPte.u & X86_PTE_PG_MASK, 216 216 iShw); … … 235 235 AssertRC(rc); 236 236 237 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK _FULL, GstPte.u & X86_PTE_PG_MASK));237 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK)); 238 238 pgmPoolTracDerefGCPhysHint(pPool, pPage, 239 239 PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), … … 326 326 AssertRC(rc); 327 327 328 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK _FULL));328 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK)); 329 329 pgmPoolTracDerefGCPhysHint(pPool, pPage, 330 330 PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), 331 GstPte.u & X86_PTE_PAE_PG_MASK _FULL,331 GstPte.u & X86_PTE_PAE_PG_MASK, 332 332 iShw); 333 333 PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0); … … 350 350 # endif 351 351 AssertRC(rc); 352 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK _FULL));352 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK)); 353 353 pgmPoolTracDerefGCPhysHint(pPool, pPage, 354 354 PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), 355 GstPte.u & X86_PTE_PAE_PG_MASK _FULL,355 GstPte.u & X86_PTE_PAE_PG_MASK, 356 356 iShw2); 357 357 PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0); … … 1014 1014 { 1015 1015 RTHCPHYS HCPhys = -1; 1016 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK _FULL, &HCPhys);1016 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys); 1017 1017 if (rc != VINF_SUCCESS) 1018 1018 { … … 1366 1366 { 1367 1367 RTHCPHYS HCPhys = NIL_RTHCPHYS; 1368 int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL, &HCPhys);1368 int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys); 1369 1369 if ( rc != VINF_SUCCESS 1370 1370 || PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys) … … 1438 1438 && pGstPT->a[i].n.u1Present) 1439 1439 { 1440 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL))1440 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK)) 1441 1441 { 1442 1442 *pfFlush = true; … … 1447 1447 { 1448 1448 /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */ 1449 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL))1449 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK)) 1450 1450 { 1451 1451 #ifdef VBOX_STRICT 1452 1452 RTHCPHYS HCPhys = NIL_RTGCPHYS; 1453 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL, &HCPhys);1453 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys); 1454 1454 AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys)); 1455 1455 #endif … … 1466 1466 /* Something was changed, so flush it. */ 1467 1467 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n", 1468 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL));1469 pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL, i);1468 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK)); 1469 pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i); 1470 1470 PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0); 1471 1471 } … … 3072 3072 3073 3073 #if 1 /** @todo FIXME r64700 regression? */ 3074 if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK _FULL| X86_PTE_P)) == u64)3074 if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64) 3075 3075 #else 3076 if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK _FULL| X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)3076 if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64) 3077 3077 #endif 3078 3078 { … … 3090 3090 #ifdef LOG_ENABLED 3091 3091 Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent)); 3092 Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK _FULL| X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX), u64));3092 Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX), u64)); 3093 3093 for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++) 3094 3094 # if 1 /** @todo FIXME r64700 regression? */ 3095 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK _FULL| X86_PTE_P)) == u64)3095 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64) 3096 3096 # else 3097 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK _FULL| X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)3097 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64) 3098 3098 # endif 3099 3099 Log(("i=%d cFound=%d\n", i, ++cFound)); … … 3461 3461 if (PGMSHWPTEPAE_IS_P(pPT->a[i])) 3462 3462 { 3463 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK _FULL| X86_PTE_P)) == u64)3463 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64) 3464 3464 { 3465 3465 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i])); … … 4146 4146 { 4147 4147 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n", 4148 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL));4149 pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK _FULL, i);4148 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK)); 4149 pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i); 4150 4150 if (!pPage->cPresent) 4151 4151 break; … … 4909 4909 * Look up the page. 4910 4910 */ 4911 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK _FULL);4911 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK); 4912 4912 4913 4913 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0)); … … 4927 4927 PVM pVM = pPool->CTX_SUFF(pVM); 4928 4928 Assert(PGMIsLockOwner(pVM)); 4929 return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK _FULL);4929 return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK); 4930 4930 } 4931 4931 -
trunk/src/VBox/VMM/VMMAll/PGMAllShw.h
r32035 r32036 135 135 # define SHW_PD_SHIFT X86_PD_PAE_SHIFT 136 136 # define SHW_PD_MASK X86_PD_PAE_MASK 137 # define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL137 # define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK 138 138 # define SHW_PTE_IS_P(Pte) PGMSHWPTEPAE_IS_P(Pte) 139 139 # define SHW_PTE_IS_RW(Pte) PGMSHWPTEPAE_IS_RW(Pte) -
trunk/src/VBox/VMM/VMMGC/PGMGCGst.h
r32034 r32036 70 70 # define GST_PD_SHIFT X86_PD_PAE_SHIFT 71 71 # define GST_PD_MASK X86_PD_PAE_MASK 72 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL72 # define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK 73 73 # define GST_PT_SHIFT X86_PT_PAE_SHIFT 74 74 # define GST_PT_MASK X86_PT_PAE_MASK -
trunk/src/VBox/VMM/VMMGC/PGMGCShw.h
r32035 r32036 61 61 # define SHW_PD_SHIFT X86_PD_PAE_SHIFT 62 62 # define SHW_PD_MASK X86_PD_PAE_MASK 63 # define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK _FULL63 # define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK 64 64 # define SHW_PT_SHIFT X86_PT_PAE_SHIFT 65 65 # define SHW_PT_MASK X86_PT_PAE_MASK -
trunk/src/VBox/VMM/VMMR0/PGMR0.cpp
r32035 r32036 91 91 Assert(pVM->pgm.s.aHandyPages[i].idSharedPage == NIL_GMM_PAGEID); 92 92 Assert(pVM->pgm.s.aHandyPages[i].HCPhysGCPhys != NIL_RTHCPHYS); 93 Assert(!(pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK _FULL));93 Assert(!(pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK)); 94 94 } 95 95 … … 136 136 Assert(pVM->pgm.s.aHandyPages[i].idSharedPage == NIL_GMM_PAGEID); 137 137 Assert(pVM->pgm.s.aHandyPages[i].HCPhysGCPhys != NIL_RTHCPHYS); 138 Assert(!(pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK _FULL));138 Assert(!(pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK)); 139 139 } 140 140 -
trunk/src/VBox/VMM/VMMRZ/PGMRZDynMap.cpp
r32035 r32036 1010 1010 RTHCPHYS HCPhysPte = pThis->fLegacyMode 1011 1011 ? pThis->paPages[iPage].uPte.pLegacy->u & X86_PTE_PG_MASK 1012 : pThis->paPages[iPage].uPte.pPae->u & X86_PTE_PAE_PG_MASK _FULL;1012 : pThis->paPages[iPage].uPte.pPae->u & X86_PTE_PAE_PG_MASK; 1013 1013 if (HCPhysPage != HCPhysPte) 1014 1014 { … … 1440 1440 X86PGPAEUINT uNew = (uOld & (X86_PTE_G | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT)) 1441 1441 | X86_PTE_P | X86_PTE_RW | X86_PTE_A | X86_PTE_D 1442 | (HCPhys & X86_PTE_PAE_PG_MASK _FULL);1442 | (HCPhys & X86_PTE_PAE_PG_MASK); 1443 1443 while (!ASMAtomicCmpXchgExU64(&paPages[iFreePage].uPte.pPae->u, uNew, uOld, &uOld)) 1444 1444 AssertMsgFailed(("uOld=%#llx uOld2=%#llx uNew=%#llx\n", uOld, uOld2, uNew)); … … 1624 1624 | (paSavedPTEs[iPage] & (X86_PTE_G | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT)) 1625 1625 #endif 1626 | (paPages[iPage].HCPhys & X86_PTE_PAE_PG_MASK _FULL);1626 | (paPages[iPage].HCPhys & X86_PTE_PAE_PG_MASK); 1627 1627 CHECK_RET(paPages[iPage].uPte.pLegacy->u == uPte, 1628 1628 ("#%u: %#x %#x", iPage, paPages[iPage].uPte.pLegacy->u, uPte)); … … 1664 1664 | (paSavedPTEs[iPage] & (X86_PTE_G | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT)) 1665 1665 #endif 1666 | (paPages[iPage].HCPhys & X86_PTE_PAE_PG_MASK _FULL);1666 | (paPages[iPage].HCPhys & X86_PTE_PAE_PG_MASK); 1667 1667 CHECK_RET(paPages[iPage].uPte.pPae->u == uPte, 1668 1668 ("#%u: %#llx %#llx", iPage, paPages[iPage].uPte.pLegacy->u, uPte)); -
trunk/src/VBox/VMM/testcase/tstCompiler.cpp
r31996 r32036 174 174 void Mix6432Consts(PX86PTEPAE64 pPteDst, PX86PTEPAE64 pPteSrc) 175 175 { 176 pPteDst->u = pPteSrc->u & ~(X86_PTE_PAE_PG_MASK _FULL| X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);176 pPteDst->u = pPteSrc->u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT); 177 177 } 178 178 … … 180 180 void Mix32Var64Const64Data(PX86PTEPAE64 pPteDst, uint32_t fMask, uint32_t fFlags) 181 181 { 182 pPteDst->u = (pPteDst->u & (fMask | X86_PTE_PAE_PG_MASK _FULL)) | (fFlags & ~X86_PTE_PAE_PG_MASK_FULL);182 pPteDst->u = (pPteDst->u & (fMask | X86_PTE_PAE_PG_MASK)) | (fFlags & ~X86_PTE_PAE_PG_MASK); 183 183 } 184 184
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