- Timestamp:
- Sep 9, 2010 10:09:21 AM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
r32293 r32335 217 217 #define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */ 218 218 #define DPUBASE(pState) (HDA_REG((pState), DPUBASE)) 219 #define DPBASE_ENABLED 1 220 #define DPBASE_ADDR_MASK (~0x7f) 219 221 220 222 #define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name) … … 1164 1166 for (i = 0; i < 8; ++i) 1165 1167 { 1166 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64DPBase + i*8, &counter, 4);1168 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter)); 1167 1169 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ", 1168 1170 i , counter)); … … 1264 1266 PHDABDLEDESC pBdle = NULL; 1265 1267 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState; 1266 uint32_t u32Counter;1267 1268 uint32_t nBytes; 1268 1269 uint32_t u32Ctl; … … 1306 1307 || !u64BaseDMA) 1307 1308 return; 1309 /* Fetch the Buffer Descriptor Entry (BDE). */ 1308 1310 fetch_bd(pState, pBdle, u64BaseDMA); 1309 while( avail 1310 && !fStop) 1311 { 1312 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + u8Strm*8, &u32Counter, 4); 1311 while( avail && !fStop) 1312 { 1313 1313 switch (src) 1314 1314 { … … 1321 1321 default: 1322 1322 nBytes = 0; 1323 fStop = true; 1323 1324 AssertMsgFailed(("Unsupported")); 1324 1325 } 1325 if ( fStop 1326 && pBdle->u32BdleCviLen != pBdle->u32BdleCviPos) 1327 break; 1326 /* Update the buffer position and handle Cyclic Buffer Length (CBL) wraparound. */ 1328 1327 *pu32Lpib += nBytes; 1329 1328 avail -= nBytes; 1330 u32Counter += nBytes; 1331 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + u8Strm*8, &u32Counter, 4); 1332 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen 1333 || *pu32Lpib == u32Lcbl) 1329 if (*pu32Lpib >= u32Lcbl) 1330 *pu32Lpib -= u32Lcbl; 1331 1332 /* Optionally write back the current DMA position. */ 1333 if (pState->u64DPBase & DPBASE_ENABLED) 1334 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), 1335 (pState->u64DPBase & DPBASE_ADDR_MASK) + u8Strm*8, pu32Lpib, sizeof(*pu32Lpib)); 1336 1337 /* Process end of buffer condition. */ 1338 if (pBdle->u32BdleCviPos == pBdle->u32BdleCviLen) 1334 1339 { 1335 if ( u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE) 1336 && ( ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen 1337 && pBdle->fBdleCviIoc ) 1338 || *pu32Lpib == u32Lcbl)) 1340 if (pBdle->fBdleCviIoc) 1339 1341 { 1340 1342 *pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS); 1341 1343 hdaProcessInterrupt(pState); 1342 if (*pu32Lpib == u32Lcbl)1343 {1344 *pu32Lpib = 0;1345 u32Counter = 0;1346 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + u8Strm*8, &u32Counter, 4);1347 }1348 1344 } 1349 if (pBdle->u32BdleCviPos == pBdle->u32BdleCviLen) 1350 { 1351 pBdle->u32BdleCviPos = 0; 1352 pBdle->u32BdleCvi++; 1353 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1) 1354 pBdle->u32BdleCvi = 0; 1355 fStop = true; /* Give the guest a chance to refill buffers. */ 1356 } 1357 else 1358 fStop = false; 1359 fetch_bd(pState, pBdle, u64BaseDMA); 1345 pBdle->u32BdleCviPos = 0; 1346 pBdle->u32BdleCvi++; 1347 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1) 1348 pBdle->u32BdleCvi = 0; 1349 fStop = true; /* Give the guest a chance to refill (or empty) buffers. */ 1350 1351 /* Read the next BDE unless we're exiting. */ 1352 if (!fStop) 1353 fetch_bd(pState, pBdle, u64BaseDMA); 1360 1354 } 1361 1355 }
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