Changeset 32477 in vbox

Timestamp:

Sep 14, 2010 1:15:01 PM (14 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

65851

Message:

PCI: BIOS & ACPI work

Location:

trunk/src/VBox

Files:

• Devices/Bus/DevPciIch9.cpp (modified) (1 diff)
• Devices/PC/BIOS/rombios.c (modified) (5 diffs)
• Devices/PC/DevACPI.cpp (modified) (5 diffs)
• Devices/PC/vbox.dsl (modified) (2 diffs)
• Main/ConsoleImpl2.cpp (modified) (4 diffs)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -1540 +1540 @@
     PCIDevSetClassSub(  &pBus->aPciDev,   0x00); /* Host/PCI bridge */
     PCIDevSetClassBase( &pBus->aPciDev,   0x06); /* bridge */
-    PCIDevSetHeaderType(&pBus->aPciDev,   0x00);
+    PCIDevSetHeaderType(&pBus->aPciDev,   0x00); /* normal device */
 
     pBus->aPciDev.pDevIns               = pDevIns;
     /* We register Host<->PCI controller on the bus */
     ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
+
+    /*
+     * Register I/O ports and save state.
+     */
+    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
+    if (RT_FAILURE(rc))
+        return rc;
+    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
+    if (RT_FAILURE(rc))
+        return rc;
+    if (fGCEnabled)
+    {
+        rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
+        if (RT_FAILURE(rc))
+            return rc;
+        rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
+        if (RT_FAILURE(rc))
+            return rc;
+    }
+    if (fR0Enabled)
+    {
+        rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
+        if (RT_FAILURE(rc))
+            return rc;
+        rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
+        if (RT_FAILURE(rc))
+            return rc;
+    }
+
 
     /** @todo: other chipset devices shall be registered too */

trunk/src/VBox/Devices/PC/BIOS/rombios.c

@@ -245 +245 @@
 // undef enables PCIBIOS when at least one PCI device is found
 // i440FX is emulated by Bochs and QEMU
-#define PCI_FIXED_HOST_BRIDGE 0x12378086 ;; i440FX PCI bridge
+#define PCI_FIXED_HOST_BRIDGE_1  0x12378086 ;; i440FX PCI bridge
+#define PCI_FIXED_HOST_BRIDGE_2  0x244e8086 ;; ICH9 PCI bridge
 
 // #20  is dec 20
@@ -9820 +9821 @@
   cmp eax, #0x49435024 ;; "$PCI"
   jne unknown_service
+
+#ifdef PCI_FIXED_HOST_BRIDGE_1
   mov eax, #0x80000000
   mov dx, #0x0cf8
@@ -9825 +9828 @@
   mov dx, #0x0cfc
   in  eax, dx
-#ifdef PCI_FIXED_HOST_BRIDGE
-  cmp eax, #PCI_FIXED_HOST_BRIDGE
-  jne unknown_service
-#else
-  ;; say ok if a device is present
-  cmp eax, #0xffffffff
-  je unknown_service
+  cmp eax, #PCI_FIXED_HOST_BRIDGE_1
+  je device_ok
 #endif
+
+#ifdef PCI_FIXED_HOST_BRIDGE_2
+  /* 0x1e << 11 */
+  mov eax, #0x8000f000
+  mov dx, #0x0cf8
+  out dx, eax
+  mov dx, #0x0cfc
+  in  eax, dx
+  cmp eax, #PCI_FIXED_HOST_BRIDGE_2
+  je device_ok
+#endif
+  jmp unknown_service
+device_ok:
   mov ebx, #0x000f0000
   mov ecx, #0
@@ -10011 +10022 @@
   push eax
   push dx
+#ifdef PCI_FIXED_HOST_BRIDGE_1
   mov eax, #0x80000000
   mov dx, #0x0cf8
@@ -10016 +10028 @@
   mov dx, #0x0cfc
   in  eax, dx
-#ifdef PCI_FIXED_HOST_BRIDGE
-  cmp eax, #PCI_FIXED_HOST_BRIDGE
-  je  pci_present
-#else
-  ;; say ok if a device is present
-  cmp eax, #0xffffffff
-  jne  pci_present
+  cmp eax, #PCI_FIXED_HOST_BRIDGE_1
+  je pci_present
+#endif
+
+#ifdef PCI_FIXED_HOST_BRIDGE_2
+  /* 0x1e << 11 */
+  mov eax, #0x8000f000
+  mov dx, #0x0cf8
+  out dx, eax
+  mov dx, #0x0cfc
+  in  eax, dx
+  cmp eax, #PCI_FIXED_HOST_BRIDGE_2
+  je pci_present
 #endif
   pop dx

trunk/src/VBox/Devices/PC/DevACPI.cpp

@@ -162 +162 @@
     SYSTEM_INFO_INDEX_NIC_ADDRESS       = 15, /**< NIC PCI address, or 0 */
     SYSTEM_INFO_INDEX_AUDIO_ADDRESS     = 16, /**< Audio card PCI address, or 0 */
-    SYSTEM_INFO_INDEX_POWER_STATES      = 17, 
+    SYSTEM_INFO_INDEX_POWER_STATES      = 17,
     SYSTEM_INFO_INDEX_IOC_ADDRESS       = 18, /**< IO controller PCI address */
-    SYSTEM_INFO_INDEX_END               = 19,
+    SYSTEM_INFO_INDEX_HBC_ADDRESS       = 19, /**< host bus controller PCI address */
+    SYSTEM_INFO_INDEX_END               = 20, 
     SYSTEM_INFO_INDEX_INVALID           = 0x80,
     SYSTEM_INFO_INDEX_VALID             = 0x200
@@ -271 +272 @@
     /** PCI address of the IO controller device. */
     uint32_t            u32IocPciAddress;
-    uint32_t            pad0;
+    /** PCI address of the host bus controller device. */
+    uint32_t            u32HbcPciAddress;
 
     /** ACPI port base interface. */
@@ -1572 +1574 @@
                     break;
 
+                case SYSTEM_INFO_INDEX_HBC_ADDRESS:
+                    *pu32 = s->u32HbcPciAddress;
+                    break;
+
                 /* This is only for compatability with older saved states that
                    may include ACPI code that read these values.  Legacy is
@@ -2465 +2471 @@
                               "AudioPciAddress\0"
                               "IocPciAddress\0"
+                              "HostBusPciAddress\0"
                               "EnableSuspendToDisk\0"
                               "PowerS1Enabled\0"
@@ -2533 +2540 @@
         return PDMDEV_SET_ERROR(pDevIns, rc,
                                 N_("Configuration error: Failed to read \"IocPciAddress\""));
+
+    /* query host bus controller PCI address */
+    rc = CFGMR3QueryU32Def(pCfg, "HostBusPciAddress", &s->u32HbcPciAddress, 0);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("Configuration error: Failed to read \"HostBusPciAddress\""));
 
     /* query whether S1 power state should be exposed */

trunk/src/VBox/Devices/PC/vbox.dsl

@@ -146 +146 @@
         HDAA,  32, // HDA PCI address
         PWRS,  32, // power states
-        IOCA,  32, // Southbridge IO controller PCI address
+        IOCA,  32, // southbridge IO controller PCI address
+        HBCA,  32, // host bus controller address 
         Offset (0x80),
         ININ, 32,
@@ -511 +512 @@
             
             Name (_HID, EisaId ("PNP0A03")) // PCI bus PNP id
-            Name (_ADR, 0x00) // address
-            Name (_BBN, 0x00) // base bus adddress
+            Method(_ADR, 0, NotSerialized)  // PCI address
+            {
+                 Return (HBCA)
+            }
+            Name (_BBN, 0x00) // base bus adddress (bus number)
             Name (_UID, 0x00)
 

trunk/src/VBox/Main/ConsoleImpl2.cpp

@@ -822 +822 @@
         ChipsetType_T chipsetType;
         hrc = pMachine->COMGETTER(ChipsetType)(&chipsetType);                                H();
-        uint32_t u32IocPciAddress;
+        uint32_t u32IocPciAddress, u32HbcPciAddress;
 
         switch (chipsetType)
@@ -830 +830 @@
             case ChipsetType_PIIX3:
                 InsertConfigNode(pDevices, "pci", &pDev);
+                u32HbcPciAddress = 0;
                 u32IocPciAddress = (0x1 << 16) | 0; // ISA controller
                 break;
             case ChipsetType_ICH9:
                 InsertConfigNode(pDevices, "ich9pci", &pDev);
+                u32HbcPciAddress = (0x1d << 16) | 0;
                 u32IocPciAddress = (0x1f << 16) | 0; // LPC controller
                 break;
@@ -877 +879 @@
         /* so always enable HPET in extended profile */
         fHpetEnabled |= fOsXGuest;
+        /* HPET is always present on ICH9 */
+        fHpetEnabled |= (chipsetType == ChipsetType_ICH9);
         if (fHpetEnabled)
         {
@@ -2279 +2283 @@
             }
             InsertConfigInteger(pCfg,  "IocPciAddress", u32IocPciAddress);
+            InsertConfigInteger(pCfg,  "HostBusPciAddress", u32HbcPciAddress);
             InsertConfigInteger(pCfg,  "ShowCpu", fShowCpu);
             InsertConfigInteger(pCfg,  "CpuHotPlug", fCpuHotPlug);