VirtualBox

Changeset 32637 in vbox for trunk/src/VBox/Devices/Bus


Ignore:
Timestamp:
Sep 20, 2010 12:41:48 PM (14 years ago)
Author:
vboxsync
Message:

PCI: further MCFG work

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r32557 r32637  
    103103    uint8_t             uBus;
    104104#endif
     105    /* Physical address of PCI config space MMIO region */
     106     uint64_t            u64PciConfigMMioAddress;
     107    /* Length of PCI config space MMIO region */
     108    uint64_t            u64PciConfigMMioLength;
    105109
    106110
     
    157161PDMBOTHCBDECL(int)  ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
    158162PDMBOTHCBDECL(int)  ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
     163PDMBOTHCBDECL(int)  ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
     164PDMBOTHCBDECL(int)  ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
    159165
    160166RT_C_DECLS_END
     
    498504
    499505#ifdef IN_RING3
     506
     507PDMBOTHCBDECL(int)  ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
     508{
     509    //PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     510    Assert(false);
     511    return VINF_IOM_MMIO_UNUSED_FF;
     512}
     513
     514PDMBOTHCBDECL(int)  ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
     515{
     516    //PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     517    Assert(false);
     518    return VINF_IOM_MMIO_UNUSED_FF;
     519}
     520
    500521DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
    501522{
     
    826847        { VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" },     // fBridge=??
    827848        { VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
    828         { VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" },    // fWritable = !? 
     849        { VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" },    // fWritable = !?
    829850        { VBOX_PCI_MAX_LAT, 1, 0, 3, "MAX_LAT" },           // fBridge=!?
    830851        /* The COMMAND register must come last as it requires the *ADDRESS*
     
    17231744     * Validate and read configuration.
    17241745     */
    1725     if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
     1746    if (!CFGMR3AreValuesValid(pCfg,
     1747                              "IOAPIC\0"
     1748                              "GCEnabled\0"
     1749                              "R0Enabled\0"
     1750                              "McfgBase\0"
     1751                              "McfgLength\0"
     1752                              ))
    17261753        return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
    17271754
     
    17461773        return PDMDEV_SET_ERROR(pDevIns, rc,
    17471774                                N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
     1775
    17481776    Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
    17491777
     
    17591787        return PDMDEV_SET_ERROR(pDevIns, rc,
    17601788                                N_("Must use IO-APIC with ICH9 chipset"));
     1789    rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
     1790    if (RT_FAILURE(rc))
     1791        return PDMDEV_SET_ERROR(pDevIns, rc,
     1792                                N_("Configuration error: Failed to read \"McfgBase\""));
     1793    rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
     1794    if (RT_FAILURE(rc))
     1795        return PDMDEV_SET_ERROR(pDevIns, rc,
     1796                                N_("Configuration error: Failed to read \"McfgLength\""));
     1797
    17611798    pGlobals->pDevInsR3 = pDevIns;
    17621799    pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     
    18431880        if (RT_FAILURE(rc))
    18441881            return rc;
     1882    }
     1883
     1884    if (pGlobals->u64PciConfigMMioAddress != 0)
     1885    {
     1886        rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, pGlobals,
     1887                                   ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, NULL, "MCFG ranges");
     1888        if (RT_FAILURE(rc))
     1889        {
     1890            AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
     1891            return rc;
     1892        }
    18451893    }
    18461894
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