Changeset 32637 in vbox for trunk/src/VBox/Devices/Bus
- Timestamp:
- Sep 20, 2010 12:41:48 PM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r32557 r32637 103 103 uint8_t uBus; 104 104 #endif 105 /* Physical address of PCI config space MMIO region */ 106 uint64_t u64PciConfigMMioAddress; 107 /* Length of PCI config space MMIO region */ 108 uint64_t u64PciConfigMMioLength; 105 109 106 110 … … 157 161 PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb); 158 162 PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb); 163 PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb); 164 PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb); 159 165 160 166 RT_C_DECLS_END … … 498 504 499 505 #ifdef IN_RING3 506 507 PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb) 508 { 509 //PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS); 510 Assert(false); 511 return VINF_IOM_MMIO_UNUSED_FF; 512 } 513 514 PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb) 515 { 516 //PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS); 517 Assert(false); 518 return VINF_IOM_MMIO_UNUSED_FF; 519 } 520 500 521 DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus) 501 522 { … … 826 847 { VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=?? 827 848 { VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" }, 828 { VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? 849 { VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? 829 850 { VBOX_PCI_MAX_LAT, 1, 0, 3, "MAX_LAT" }, // fBridge=!? 830 851 /* The COMMAND register must come last as it requires the *ADDRESS* … … 1723 1744 * Validate and read configuration. 1724 1745 */ 1725 if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0")) 1746 if (!CFGMR3AreValuesValid(pCfg, 1747 "IOAPIC\0" 1748 "GCEnabled\0" 1749 "R0Enabled\0" 1750 "McfgBase\0" 1751 "McfgLength\0" 1752 )) 1726 1753 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES; 1727 1754 … … 1746 1773 return PDMDEV_SET_ERROR(pDevIns, rc, 1747 1774 N_("Configuration error: Failed to query boolean value \"R0Enabled\"")); 1775 1748 1776 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled)); 1749 1777 … … 1759 1787 return PDMDEV_SET_ERROR(pDevIns, rc, 1760 1788 N_("Must use IO-APIC with ICH9 chipset")); 1789 rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0); 1790 if (RT_FAILURE(rc)) 1791 return PDMDEV_SET_ERROR(pDevIns, rc, 1792 N_("Configuration error: Failed to read \"McfgBase\"")); 1793 rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0); 1794 if (RT_FAILURE(rc)) 1795 return PDMDEV_SET_ERROR(pDevIns, rc, 1796 N_("Configuration error: Failed to read \"McfgLength\"")); 1797 1761 1798 pGlobals->pDevInsR3 = pDevIns; 1762 1799 pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); … … 1843 1880 if (RT_FAILURE(rc)) 1844 1881 return rc; 1882 } 1883 1884 if (pGlobals->u64PciConfigMMioAddress != 0) 1885 { 1886 rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, pGlobals, 1887 ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, NULL, "MCFG ranges"); 1888 if (RT_FAILURE(rc)) 1889 { 1890 AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc)); 1891 return rc; 1892 } 1845 1893 } 1846 1894
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