Index: /trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
===================================================================
--- /trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp	(revision 32764)
+++ /trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp	(revision 32765)
@@ -1674,61 +1674,75 @@
     PCIDevSetSubSystemId        (&pThis->dev, 0x0000); /* 2e ro. */
     PCIDevSetInterruptLine      (&pThis->dev, 0x00);   /* 3c rw. */
-    PCIDevSetInterruptPin       (&pThis->dev, 0x01);   /* 3d ro - INTA#. */             Assert (pThis->dev.config[0x3d] == 0x01);
-    PCIDevSetCapabilityList(&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
+    PCIDevSetInterruptPin       (&pThis->dev, 0x01);   /* 3d ro - INTA#. */
+
+//#define HDA_AS_PCI_EXPRESS
+
+#ifdef HDA_AS_PCI_EXPRESS
+    PCIDevSetCapabilityList     (&pThis->dev, 0x80);
+#else
+    PCIDevSetCapabilityList     (&pThis->dev, 0x50);   /* ICH6 datasheet 18.1.16 */
+#endif
 
     //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
     // of these values needs to be properly documented!
     /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
-    pThis->dev.config[0x40] = 0x01;
-
-    pThis->dev.config[0x50] = VBOX_PCI_CAP_ID_PM;
-    pThis->dev.config[0x51] = 0x00; /* next */
-    pThis->dev.config[0x52] = VBOX_PCI_PM_CAP_DSI | 0x02;
-    pThis->dev.config[0x53] = 0x00; /* PM - disabled,  */
-
-#if 0
-    pThis->dev.config[0x60] = VBOX_PCI_CAP_ID_MSI;
-    pThis->dev.config[0x61] = 0x70; /* next */
-    pThis->dev.config[0x62] = 0x00;
-    pThis->dev.config[0x63] = VBOX_PCI_MSIX_FLAGS_ENABLE >> 8;
+    PCIDevSetByte(&pThis->dev, 0x40, 0x01);
+
+    /* Power Management */
+    PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
+    PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
+    PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
+
+#ifdef HDA_AS_PCI_EXPRESS
+    /* Message Signalled Interrupts, up to 28 bytes */
+    PCIDevSetByte(&pThis->dev,  0x60 + 0, VBOX_PCI_CAP_ID_MSI);
+    PCIDevSetByte(&pThis->dev,  0x60 + 1, 0x50); /* next */
+    PCIDevSetWord(&pThis->dev,  0x60 + 2, 0 ? VBOX_PCI_MSIX_FLAGS_ENABLE : 0);
+    /* Physical address of MSI, could be 64-bit if VBOX_PCI_MSI_FLAGS_64BIT */
+    PCIDevSetDWord(&pThis->dev, 0x60 + 4, 0 ? 0x00000001 : 0);
 #endif
 
-#if 0
-    pThis->dev.config[0x90] = VBOX_PCI_CAP_ID_EXP; /* PCI_Express */
-    pThis->dev.config[0x90+1] = 0x50; /* next */
+#ifdef HDA_AS_PCI_EXPRESS
+    /* PCI Express */
+    PCIDevSetByte  (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
+    PCIDevSetByte  (&pThis->dev, 0x80 + 1, 0x60); /* next */
     /* Device flags */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 2, /* version */ 0x1);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 2,
+                    /* version */ 0x1     |
+                    /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
+                    /* MSI */ (100) << 9
+                    );
     /* Device capabilities */
-    PCIDevSetDWord (&pThis->dev, 0x90 + 4, 0);
+    PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
     /* Device control */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 8, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 8, 0);
     /* Device status */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 10, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 10, 0);
     /* Link caps */
-    PCIDevSetDWord (&pThis->dev, 0x90 + 12, 0);
+    PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
     /* Link control */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 16, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 16, 0);
     /* Link status */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 18, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 18, 0);
     /* Slot capabilities */
-    PCIDevSetDWord (&pThis->dev, 0x90 + 20, 0);
+    PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
     /* Slot control */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 24, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 24, 0);
     /* Slot status */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 26, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 26, 0);
     /* Root control */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 28, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 28, 0);
     /* Root capabilities */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 30, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 30, 0);
     /* Root status */
-    PCIDevSetDWord (&pThis->dev, 0x90 + 32, 0);
+    PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
     /* Device capabilities 2 */
-    PCIDevSetDWord (&pThis->dev, 0x90 + 36, 0);
+    PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
     /* Device control 2 */
-    PCIDevSetQWord (&pThis->dev, 0x90 + 40, 0);
+    PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
     /* Link control 2 */
-    PCIDevSetQWord (&pThis->dev, 0x90 + 48, 0);
+    PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
     /* Slot control 2 */
-    PCIDevSetWord  (&pThis->dev, 0x90 + 56, 0);
+    PCIDevSetWord  (&pThis->dev, 0x80 + 56, 0);
 #endif
 
Index: /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
===================================================================
--- /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 32764)
+++ /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 32765)
@@ -184,6 +184,7 @@
 // See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
 // mapping, we take n=8 approach
-DECLINLINE(void) ich9pciPhysToPciAddr(RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
-{
+DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
+{
+    GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
     pPciAddr->iBus          = (GCPhysAddr >> 20) & ((1<<8)       - 1);
     pPciAddr->iDeviceFunc   = (GCPhysAddr >> 15) & ((1<<(5+3))   - 1); // 5 bits - device, 3 bits - function
@@ -288,4 +289,11 @@
 static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
 {
+
+    if (pAddr->iRegister > 0xff)
+    {
+        LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
+        return 0;
+    }
+
     if (pAddr->iBus != 0)
     {
@@ -367,4 +375,12 @@
 static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
 {
+    if (pPciAddr->iRegister > 0xff)
+    {
+        LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
+        *pu32 = 0;
+        return 0;
+    }
+
+
     if (pPciAddr->iBus != 0)
     {
@@ -536,5 +552,5 @@
     uint32_t u32 = 0;
 
-    ich9pciPhysToPciAddr(GCPhysAddr, &aDest);
+    ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
 
     PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
@@ -556,5 +572,4 @@
     int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
     PCI_UNLOCK(pDevIns);
-    Assert(false);
 
     return rc;
@@ -567,5 +582,5 @@
     uint32_t    rv = 0;
 
-    ich9pciPhysToPciAddr(GCPhysAddr, &aDest);
+    ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
 
     PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
@@ -591,5 +606,4 @@
     PCI_UNLOCK(pDevIns);
 
-    Assert(false);
     return rc;
 }
Index: /trunk/src/VBox/Devices/PC/DevACPI.cpp
===================================================================
--- /trunk/src/VBox/Devices/PC/DevACPI.cpp	(revision 32764)
+++ /trunk/src/VBox/Devices/PC/DevACPI.cpp	(revision 32765)
@@ -1018,5 +1018,5 @@
 
 /** MMCONFIG PCI config space access (MCFG) descriptor */
-static void acpiSetupMCFG(ACPIState *s, RTGCPHYS32 addr, uint8_t    u8StartBus, uint8_t    u8EndBus)
+static void acpiSetupMCFG(ACPIState *s, RTGCPHYS32 addr)
 {
     struct {
@@ -1024,4 +1024,7 @@
         ACPITBLMCFGENTRY  entry;
     } tbl;
+
+    uint8_t    u8StartBus = 0;
+    uint8_t    u8EndBus   = (s->u64PciConfigMMioLength >> 20) - 1;
 
     memset(&tbl, 0, sizeof(tbl));
@@ -2322,5 +2325,5 @@
     if (s->fUseMcfg)
     {
-        acpiSetupMCFG(s, GCPhysMcfg + addend, 0, 255);
+        acpiSetupMCFG(s, GCPhysMcfg + addend);
         aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
         aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
Index: /trunk/src/VBox/Main/ConsoleImpl2.cpp
===================================================================
--- /trunk/src/VBox/Main/ConsoleImpl2.cpp	(revision 32764)
+++ /trunk/src/VBox/Main/ConsoleImpl2.cpp	(revision 32765)
@@ -538,7 +538,9 @@
     if (chipsetType == ChipsetType_ICH9)
     {
-        u64McfgLength = 0x10000000;
+        /* We'd better have 0x10000000 region, to cover 256 buses
+           but this put too much load on hypervisor heap */
+        u64McfgLength = 0x4000000; //0x10000000;
         cbRamHole += u64McfgLength;
-        u64McfgBase = _4G -  cbRamHole;
+        u64McfgBase = _4G - cbRamHole;
     }
 
@@ -852,4 +854,9 @@
         InsertConfigNode(pInst,    "Config", &pCfg);
         InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
+        if (chipsetType == ChipsetType_ICH9)
+        {
+            InsertConfigInteger(pCfg,  "McfgBase",   u64McfgBase);
+            InsertConfigInteger(pCfg,  "McfgLength", u64McfgLength);
+        }
 
 #if 0 /* enable this to test PCI bridging */
