Changeset 32820 in vbox for trunk/src/VBox/Devices/Bus

Timestamp:

Sep 29, 2010 4:25:16 PM (14 years ago)

Author:

vboxsync

Message:

PCI, PDM: initial drop of MSI support

Location:

trunk/src/VBox/Devices/Bus

Files:

• DevPCI.cpp (modified) (1 diff)
• DevPciIch9.cpp (modified) (13 diffs)
• MsiCommon.cpp (added)
• MsiCommon.h (added)
• PCIInternal.h (modified) (2 diffs)

trunk/src/VBox/Devices/Bus/DevPCI.cpp

@@ -2412 +2412 @@
     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
     PciBusReg.pfnRegisterR3           = pcibridgeRegister;
+    PciBusReg.pfnRegisterMsiR3        = NULL;
     PciBusReg.pfnIORegionRegisterR3   = pciIORegionRegister;
     PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -23 +23 @@
 #define PCI_INCLUDE_PRIVATE
 #include <VBox/pci.h>
+#include <VBox/msi.h>
 #include <VBox/pdmdev.h>
 #include <iprt/asm.h>
@@ -29 +30 @@
 
 #include "../Builtins.h"
+
+#include "MsiCommon.h"
 
 /**
@@ -176 +179 @@
 #ifdef IN_RING3
 static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
-static void ich9pciUpdateMappings(PCIDevice *d);
+static void ich9pciUpdateMappings(PCIDevice *pDev);
 static DECLCALLBACK(uint32_t) ich9pciConfigRead(PCIDevice *aDev, uint32_t u32Address, unsigned len);
 DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
@@ -183 +186 @@
 
 // See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
-// mapping, we take n=8 approach
+// mapping, we take n=6 approach
 DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
 {
@@ -523 +526 @@
 static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
 {
+    if (MSIIsEnabled(pPciDev))
+    {
+        Log2(("Raise a MSI interrupt: %d\n", iIrq));
+        MSINotify(pGlobals->aPciBus.CTX_SUFF(pDevIns), pPciDev, iIrq);
+        return;
+    }
+
     PPCIBUS     pBus =     &pGlobals->aPciBus;
     const bool  fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
@@ -769 +779 @@
 }
 
+
+static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
+{
+    return MSIInit(pPciDev, pMsiReg);
+}
+
+
 static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
 {
 
     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
-    
+
     /*
      * Check input.
@@ -1574 +1591 @@
     }
 
+    if (   PCIIsMsiCapable(aDev)
+        && (u32Address >= aDev->Int.s.u8MsiCapOffset)
+        && (u32Address <  aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
+       )
+    {
+        return MSIPciConfigRead(aDev, u32Address, len);
+    }
+
     AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
                     0);
@@ -1579 +1604 @@
     {
         case 1:
-            return aDev->config[u32Address];
+            return PCIDevGetByte(aDev,  u32Address);
         case 2:
-            return RT_LE2H_U16(*(uint16_t *)(aDev->config + u32Address));
+            return PCIDevGetWord(aDev,  u32Address);
         default:
         case 4:
-            return RT_LE2H_U32(*(uint32_t *)(aDev->config + u32Address));
+            return PCIDevGetDWord(aDev, u32Address);
     }
 }
@@ -1602 +1627 @@
 
     AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
+
+    if (   PCIIsMsiCapable(aDev)
+        && (u32Address >= aDev->Int.s.u8MsiCapOffset)
+        && (u32Address <  aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
+       )
+    {
+        MSIPciConfigWrite(aDev, u32Address, val, len);
+        return;
+    }
+
 
     /* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
@@ -1628 +1663 @@
             val |= pRegion->type;
         }
-        *(uint32_t *)(aDev->config + u32Address) = RT_H2LE_U32(val);
+        PCIDevSetDWord(aDev, u32Address, val);
         ich9pciUpdateMappings(aDev);
         return;
@@ -1644 +1679 @@
                 switch (addr)
                 {
-                    /* Read-only registers, see  */
+                    /* Read-only registers  */
                     case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
                     case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
@@ -1992 +2027 @@
     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
     PciBusReg.pfnRegisterR3           = ich9pciRegister;
+    PciBusReg.pfnRegisterMsiR3        = ich9pciRegisterMsi;
     PciBusReg.pfnIORegionRegisterR3   = ich9pciIORegionRegister;
     PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
@@ -2181 +2217 @@
     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
     PciBusReg.pfnRegisterR3           = ich9pcibridgeRegister;
+    PciBusReg.pfnRegisterMsiR3        = ich9pciRegisterMsi;
     PciBusReg.pfnIORegionRegisterR3   = ich9pciIORegionRegister;
     PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;

trunk/src/VBox/Devices/Bus/PCIInternal.h

@@ -75 +75 @@
     /** Set if the specific device fun was requested by PDM.
      * If clear the device and it's functions can be relocated to satisfy the slot request of another device. */
-    PCIDEV_FLAG_REQUESTED_DEVFUNC = 1<<0,
+    PCIDEV_FLAG_REQUESTED_DEVFUNC  = 1<<0,
     /** Flag whether the device is a pci-to-pci bridge.
      * This is set prior to device registration.  */
-    PCIDEV_FLAG_PCI_TO_PCI_BRIDGE = 1<<1,
+    PCIDEV_FLAG_PCI_TO_PCI_BRIDGE  = 1<<1,
     /** Flag whether the device is a PCI Express device.
      * This is set prior to device registration.  */
     PCIDEV_FLAG_PCI_EXPRESS_DEVICE = 1<<2,
     /** Flag whether the device is capable of MSI.
-     * This is set prior to device registration.  */
-    PCIDEV_FLAG_PCI_MSI            = 1<<3,
-     /** Flag whether the device is capable of MSI-X.
-     * This is set prior to device registration.  */
-    PCIDEV_FLAG_PCI_MSIX           = 1<<4
-    
+     * This one is set by analyzing device capabilities, or explicitly.  */
+    PCIDEV_FLAG_MSI_CAPABLE        = 1<<3,
+    /** Flag whether the device is capable of MSI-X.
+     * This one is set by analyzing device capabilities.  */
+    PCIDEV_FLAG_MSIX_CAPABLE       = 1<<4
 };
 
@@ -118 +117 @@
     int32_t                         uIrqPinState;
 
+    /* Offset of MSI PCI capability in config space, or 0 */
+    uint8_t                         u8MsiCapOffset;
+    /* Size of MSI PCI capability in config space, or 0 */
+    uint8_t                         u8MsiCapSize;
+    /* Offset of MSI-X PCI capability in config space, or 0 */
+    uint8_t                         u8MsixCapOffset;
+    /* Size of MSI-X PCI capability in config space, or 0 */
+    uint8_t                         u8MsixCapSize;
+
+    uint32_t                        Alignment1;
+
     /** Read config callback for PCI bridges to pass requests
      *  to devices on another bus.