Changeset 32935 in vbox for trunk/src/VBox/Devices/Bus

Timestamp:

Oct 6, 2010 9:28:42 AM (14 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

66421

Message:

PDM, VMM, PCI: reworked MSI API: now MSIs delivered via IOAPIC API, not with MMIO access, LSI logic now can work in MSI mode

Location:

trunk/src/VBox/Devices/Bus

Files:

• DevPciIch9.cpp (modified) (4 diffs)
• MsiCommon.cpp (modified) (8 diffs)
• MsiCommon.h (modified) (1 diff)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -528 +528 @@
 static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
 {
-    if (MSIIsEnabled(pPciDev))
+    if (MsiIsEnabled(pPciDev))
     {
         Log2(("Raise a MSI interrupt: %d\n", iIrq));
         /* We only trigger MSI on level up, as technically it's matching flip-flop best (maybe even assert that level == PDM_IRQ_LEVEL_FLIP_FLOP) */
         if ((iLevel & PDM_IRQ_LEVEL_HIGH) != 0)
-            MSINotify(pGlobals->aPciBus.CTX_SUFF(pDevIns), pPciDev, iIrq);
+        {
+            PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
+            MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq);
+        }
         return;
     }
@@ -786 +789 @@
 static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
 {
-    return MSIInit(pPciDev, pMsiReg);
+    return MsiInit(pPciDev, pMsiReg);
 }
 
@@ -1686 +1689 @@
        )
     {
-        return MSIPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
+        return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
     }
 
@@ -1723 +1726 @@
        )
     {
-        MSIPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, val, len);
+        MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
+                          aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
+                          aDev, u32Address, val, len);
         return;
     }

trunk/src/VBox/Devices/Bus/MsiCommon.cpp

@@ -92 +92 @@
 
 
-void     MSIPciConfigWrite(PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len)
+void     MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len)
 {
     int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
@@ -113 +113 @@
                 /* don't change read-only bits: 1-3,7 */
                 val &= UINT32_C(~0x8e);
-                pDev->config[uAddr] &= ~val;
+                pDev->config[uAddr] = val;
                 break;
             case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
@@ -149 +149 @@
                                 /* To ensure that we're no longer masked */
                                 pDev->config[uAddr] &= ~iBit;
-                                MSINotify(pDevIns, pDev, maskUpdated*8 + iBitNum);
+                                MsiNotify(pDevIns, pPciHlp, pDev, maskUpdated*8 + iBitNum);
                             }
                         }
@@ -162 +162 @@
 }
 
-uint32_t MSIPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len)
+uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len)
 {
     int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
@@ -172 +172 @@
     {
         case 1:
-            rv = PCIDevGetByte(pDev, u32Address);
+            rv = PCIDevGetByte(pDev,  u32Address);
             break;
         case 2:
-            rv = PCIDevGetWord(pDev, u32Address);
+            rv = PCIDevGetWord(pDev,  u32Address);
             break;
         case 4:
@@ -190 +190 @@
 
 
-int MSIInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg)
+int MsiInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg)
 {
     uint16_t   cVectors    = pMsiReg->cVectors;
@@ -225 +225 @@
 
 
-bool     MSIIsEnabled(PPCIDEVICE pDev)
+bool     MsiIsEnabled(PPCIDEVICE pDev)
 {
     return PCIIsMsiCapable(pDev) && msiIsEnabled(pDev);
 }
 
-void MSINotify(PPDMDEVINS pDevIns, PPCIDEVICE pDev, int iVector)
+void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector)
 {
     Log2(("MSINotify: %d\n", iVector));
@@ -250 +250 @@
     *upPending &= ~(1<<iVector);
 
-    PDMDevHlpPhysWrite(pDevIns, GCAddr, &u32Value, sizeof(u32Value));
-}
+    Assert(pPciHlp->pfnIoApicSendMsi != NULL);
+    pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value);
+}

trunk/src/VBox/Devices/Bus/MsiCommon.h

@@ -15 +15 @@
  */
 
+/* Maybe belongs to types.h */
+#ifdef IN_RING3
+typedef PCPDMPCIHLPR3 PCPDMPCIHLP;
+#endif
+
+#ifdef IN_RING0
+typedef PCPDMPCIHLPR0 PCPDMPCIHLP;
+#endif
+
+#ifdef IN_RC
+typedef PCPDMPCIHLPRC PCPDMPCIHLP;
+#endif
+
 /* Init MSI support in the device. */
-int      MSIInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg);
+int      MsiInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg);
 
 /* If MSI is enabled, so that MSINotify() shall be used for notifications.  */
-bool     MSIIsEnabled(PPCIDEVICE pDev);
+bool     MsiIsEnabled(PPCIDEVICE pDev);
+
 /* Device notification (aka interrupt). */
-void     MSINotify(PPDMDEVINS pDevIns, PPCIDEVICE pDev, int iVector);
+void     MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector);
 
 /* PCI config space accessors for MSI registers */
-void     MSIPciConfigWrite(PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len);
-uint32_t MSIPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len);
+void     MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len);
+uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len);