Changeset 33049 in vbox for trunk/src/VBox/Devices/EFI/Firmware2

Timestamp:

Oct 12, 2010 2:29:32 AM (14 years ago)

Author:

vboxsync

Message:

EFI: right port assignments.

File:

• trunk/src/VBox/Devices/EFI/Firmware2/VBoxPkg/VBoxIdeBusDxe/Ide.c (modified) (4 diffs)

trunk/src/VBox/Devices/EFI/Firmware2/VBoxPkg/VBoxIdeBusDxe/Ide.c

@@ -337 +337 @@
     return Status;
   }
-  DEBUG((DEBUG_INFO, "class code: %x\n", PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE));
+  DEBUG((DEBUG_INFO, "class primary code: %x\n", PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE));
+  DEBUG((DEBUG_INFO, "class secondary code: %x\n", PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE));
   if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {
     switch (PciSubClass)
@@ -376 +377 @@
           break;
        case 0x6:
-          IdeRegsBaseAddr[IdePrimary].CommandBlockBaseAddr  = 0x1e8;
-          IdeRegsBaseAddr[IdePrimary].ControlBlockBaseAddr  = 0x3e6;
-          IdeRegsBaseAddr[IdePrimary].BusMasterBaseAddr     = 0;
+          IdeRegsBaseAddr[IdePrimary].CommandBlockBaseAddr  = 0x168;
+          IdeRegsBaseAddr[IdePrimary].ControlBlockBaseAddr  = 0x366;
+          IdeRegsBaseAddr[IdePrimary].BusMasterBaseAddr     = 0;
           break;
         default:
@@ -395 +396 @@
           break;
        case 0x6:
+          IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr  = 0x1e8;
+          IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr  = 0x3e6;
+          IdeRegsBaseAddr[IdeSecondary].BusMasterBaseAddr     = 0;
+          break;
+        default:
+          ASSERT_EFI_ERROR((EFI_UNSUPPORTED)); 
+    }
+  } else {
+    //
+    // The BARs should be of IO type
+    //
+    if ((PciData.Device.Bar[2] & BIT0) == 0 ||
+        (PciData.Device.Bar[3] & BIT0) == 0) {
+      DEBUG((DEBUG_INFO, "%a:%d\n", __FILE__, __LINE__));
+      return EFI_UNSUPPORTED;
+    }
+
+    switch (PciSubClass)
+    {
+       case PCI_CLASS_MASS_STORAGE_IDE:
+          IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr  =
+          (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);
+          IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr  =
+          (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);
+          IdeRegsBaseAddr[IdeSecondary].BusMasterBaseAddr     =
+          (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
+          break;
+        case 0x6:
           IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr  = 0x168;
           IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr  = 0x366;
@@ -401 +430 @@
         default:
           ASSERT_EFI_ERROR((EFI_UNSUPPORTED)); 
-    }
-  } else {
-    //
-    // The BARs should be of IO type
-    //
-    if ((PciData.Device.Bar[2] & BIT0) == 0 ||
-        (PciData.Device.Bar[3] & BIT0) == 0) {
-      DEBUG((DEBUG_INFO, "%a:%d\n", __FILE__, __LINE__));
-      return EFI_UNSUPPORTED;
-    }
-
-    IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr  =
-    (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);
-    IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr  =
-    (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);
-    IdeRegsBaseAddr[IdeSecondary].BusMasterBaseAddr     =
-    (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
+     }
   }