Changeset 33127 in vbox for trunk/src

Timestamp:

Oct 14, 2010 11:15:16 AM (14 years ago)

Author:

vboxsync

Message:

PCI: bits

Location:

trunk/src/VBox

Files:

• Devices/Bus/DevPciIch9.cpp (modified) (21 diffs)
• Main/ConsoleImpl2.cpp (modified) (1 diff)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -69 +69 @@
 
 
-/** @def PCI_IRQ_PINS
- * Number of pins for interrupts (PIRQ#0...PIRQ#3)
- */
-#define PCI_IRQ_PINS 4
-
 /** @def PCI_APIC_IRQ_PINS
  * Number of pins for interrupts if the APIC is used.
@@ -467 +462 @@
 
 /* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
-static inline int ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
+DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
 {
     return (irq_num + uSlot) & 7;
@@ -473 +468 @@
 
 /* Add one more level up request on APIC input line */
-static inline void ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
+DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
 {
     ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
@@ -479 +474 @@
 
 /* Remove one level up request on APIC input line */
-static inline void ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
+DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
 {
     ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
@@ -649 +644 @@
                   ("Device is not a PCI bridge but on the list of PCI bridges\n"));
 
-        if (   iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
-            && iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
+        if (   iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS)
+            && iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS))
             return pBridgeTemp;
     }
@@ -658 +653 @@
 }
 
-static inline uint32_t ich9pciGetRegionReg(int iRegion)
+DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
 {
     return (iRegion == PCI_ROM_SLOT) ?
@@ -728 +723 @@
                 {
                     /* Port IO */
-                    int devclass;
-                    /* NOTE: specific hack for IDE in PC case:
-                       only one byte must be mapped. */
-                    /// @todo: do we need it?
-                    devclass = pDev->config[0x0a] | (pDev->config[0x0b] << 8);
-                    if (devclass == 0x0101 && iRegionSize == 4)
-                    {
-                        rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr + 2, 1);
-                        AssertRC(rc);
-                    }
-                    else
-                    {
-                        rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
-                        AssertRC(rc);
-                    }
+                    rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
+                    AssertRC(rc);
                 }
                 else
@@ -855 +837 @@
     uint32_t u32Value   =   (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
                           | (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
-    *(uint32_t *)(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
+    PCIDevSetDWord(pPciDev, u32Address, u32Value);
 
     return VINF_SUCCESS;
@@ -1301 +1283 @@
 
         /* match the vendor id assuming that this will never be changed. */
-        if (    DevTmp.config[0] != pDev->config[0]
-            ||  DevTmp.config[1] != pDev->config[1])
+        if (    PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
             return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
-                                     i, pDev->name, DevTmp.config, pDev->config);
+                                     i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
 
         /* commit the loaded device config. */
@@ -1372 +1353 @@
 static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
 {
-    /* Set destination address */
-    /// @todo: device locking?
-    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
-                           (uDevFn << 8) | (addr & ~3);
     uint32_t u32Val;
-    int rc = ich9pciDataRead(pGlobals, addr & 3, len, &u32Val);
+    PciAddress aPciAddr;
+
+    aPciAddr.iBus = uBus;
+    aPciAddr.iDeviceFunc = uDevFn;
+    aPciAddr.iRegister = addr;
+
+    int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val);
     AssertRC(rc);
     switch (len)
@@ -1393 +1376 @@
 static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
 {
-    /* Set destination address */
-    /// @todo: device locking?
-    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
-                           (uDevFn << 8) | addr;
-    ich9pciDataWrite(pGlobals, 0, val, len);
+    PciAddress aPciAddr;
+
+    aPciAddr.iBus = uBus;
+    aPciAddr.iDeviceFunc = uDevFn;
+    aPciAddr.iRegister = addr;
+
+    ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
 }
 
@@ -1624 +1609 @@
             cBridgeDepth--;
         }
-#if 0
-        uPin = pci_slot_get_pirq(uDevFn, pin);
-        pic_irq = pci_irqs[pin];
-        ich9pciConfigWrite(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
-#endif
     }
 }
@@ -1814 +1794 @@
                 break;
             default:
-            case 0x01: /* bridge */
+            case 0x01: /* PCI-PCI bridge */
                 switch (addr)
                 {
@@ -1842 +1822 @@
             case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
                 fUpdateMappings = true;
-                aDev->config[addr] = u8Val;
+                PCIDevSetByte(aDev, addr, u8Val);
                 break;
             case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
@@ -1848 +1828 @@
                 u8Val &= UINT32_C(~0xf8);
                 fUpdateMappings = true;
-                aDev->config[addr] = u8Val;
+                PCIDevSetByte(aDev, addr, u8Val);
                 break;
             case VBOX_PCI_STATUS:  /* Status register, bits 0-7. */
@@ -1864 +1844 @@
             default:
                 if (fWritable)
-                    aDev->config[addr] = u8Val;
+                    PCIDevSetByte(aDev, addr, u8Val);
         }
         addr++;
@@ -1921 +1901 @@
     /* Otherwise when assigning a slot, we need to make sure all its functions are available */
     for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
+    {
         if (        !pBus->apDevices[iPos]
                 &&  !pBus->apDevices[iPos + 1]
@@ -1933 +1914 @@
             return iPos;
         }
+    }
 
     return -1;
@@ -1975 +1957 @@
         PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
     {
-        /*
-         * Smth like hasHardAssignedDevsInSlot(pBus, iDev >> 3) shall be use to make
-         * it compatible with DevPCI.cpp version, but this way we cannot assign
-         * in accordance with the chipset spec.
-         */
         AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
                                  pszName, pBus->apDevices[iDev]->name, iDev));
@@ -2284 +2261 @@
     if (!PCIIsPci2PciBridge(pDev))
     {
-        pDev->config[VBOX_PCI_CACHE_LINE_SIZE] = 0x0;
-        pDev->config[VBOX_PCI_INTERRUPT_LINE] = 0x0;
+        PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
+        PCIDevSetByte(pDev, VBOX_PCI_INTERRUPT_LINE,  0x0);
     }
     /* Regions ? */
@@ -2460 +2437 @@
 
     /* Reset config space to default values. */
-    pBus->aPciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
-    pBus->aPciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
-    pBus->aPciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
+    PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
+    PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
+    PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
 }
 

trunk/src/VBox/Main/ConsoleImpl2.cpp

@@ -855 +855 @@
             case ChipsetType_PIIX3:
                 InsertConfigNode(pDevices, "pci", &pDev);
-                u32HbcPciAddress = 0;
+                u32HbcPciAddress = (0x0 << 16) | 0;
                 u32IocPciAddress = (0x1 << 16) | 0; // ISA controller
                 break;