Index: /trunk/src/VBox/Devices/Storage/DevAHCI.cpp
===================================================================
--- /trunk/src/VBox/Devices/Storage/DevAHCI.cpp	(revision 34008)
+++ /trunk/src/VBox/Devices/Storage/DevAHCI.cpp	(revision 34009)
@@ -635,5 +635,6 @@
      * a port is entering the idle state. */
     bool volatile                   fSignalIdle;
-    bool                            afAlignment8[1];
+    /** Flag whether the controller has BIOS access enabled. */
+    bool                            fBootable;
 
     /** Number of usable ports on this controller. */
@@ -6696,7 +6697,8 @@
     }
 
-    for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
-        if (!ataControllerIsIdle(&pThis->aCts[i]))
-            return false;
+    if (pThis->fBootable)
+        for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
+            if (!ataControllerIsIdle(&pThis->aCts[i]))
+                return false;
 
     return true;
@@ -7406,6 +7408,7 @@
 
     Log(("%s:\n", __FUNCTION__));
-    for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
-        ataControllerResume(&pAhci->aCts[i]);
+    if (pAhci->fBootable)
+        for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
+            ataControllerResume(&pAhci->aCts[i]);
     return;
 }
@@ -7593,6 +7596,7 @@
         ahciPortHwReset(&pAhci->ahciPort[i]);
 
-    for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
-        ataControllerReset(&pAhci->aCts[i]);
+    if (pAhci->fBootable)
+        for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
+            ataControllerReset(&pAhci->aCts[i]);
     return VINF_SUCCESS;
 }
@@ -7664,11 +7668,12 @@
      */
     if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
-                                          "R0Enabled\0"
-                                          "PrimaryMaster\0"
-                                          "PrimarySlave\0"
-                                          "SecondaryMaster\0"
-                                          "SecondarySlave\0"
-                                          "PortCount\0"
-                                          "UseAsyncInterfaceIfAvailable\0"))
+                                    "R0Enabled\0"
+                                    "PrimaryMaster\0"
+                                    "PrimarySlave\0"
+                                    "SecondaryMaster\0"
+                                    "SecondarySlave\0"
+                                    "PortCount\0"
+                                    "UseAsyncInterfaceIfAvailable\0"
+                                    "Bootable\0"))
         return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
                                 N_("AHCI configuration error: unknown option specified"));
@@ -7704,4 +7709,9 @@
         return PDMDEV_SET_ERROR(pDevIns, rc,
                                 N_("AHCI configuration error: failed to read UseAsyncInterfaceIfAvailable as boolean"));
+
+    rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &pThis->fBootable, true);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("AHCI configuration error: failed to read Bootable as boolean"));
 
     pThis->fR0Enabled = fR0Enabled;
@@ -7801,5 +7811,5 @@
                                 N_("AHCI cannot register PCI memory region for registers"));
 
-    rc = PDMDevHlpCritSectInit(pDevIns, &pThis->lock, RT_SRC_POS, "AHCI");
+    rc = PDMDevHlpCritSectInit(pDevIns, &pThis->lock, RT_SRC_POS, "AHCI%d", pDevIns->iInstance);
     if (RT_FAILURE(rc))
     {
@@ -8050,98 +8060,101 @@
     }
 
-    /*
-     * Setup IDE emulation.
-     * We only emulate the I/O ports but not bus master DMA.
-     * If the configuration values are not found the setup of the ports is as follows:
-     *     Primary Master:   Port 0
-     *     Primary Slave:    Port 1
-     *     Secondary Master: Port 2
-     *     Secondary Slave:  Port 3
-     */
-
-    /*
-     * Setup I/O ports for the PCI device.
-     */
-    pThis->aCts[0].irq          = 12;
-    pThis->aCts[0].IOPortBase1  = 0x1e8;
-    pThis->aCts[0].IOPortBase2  = 0x3e6;
-    pThis->aCts[1].irq          = 11;
-    pThis->aCts[1].IOPortBase1  = 0x168;
-    pThis->aCts[1].IOPortBase2  = 0x366;
-
-    for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
-    {
-        PAHCIATACONTROLLER pCtl = &pThis->aCts[i];
-        uint32_t iPortMaster, iPortSlave;
-        uint32_t cbSSMState = 0;
-        static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
-        {
-            { "PrimaryMaster", "PrimarySlave" },
-            { "SecondaryMaster", "SecondarySlave" }
-        };
-
-        rc = CFGMR3QueryU32Def(pCfg, s_apszDescs[i][0], &iPortMaster, 2 * i);
-        if (RT_FAILURE(rc))
-            return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
-                                       N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][0]);
-
-        rc = CFGMR3QueryU32Def(pCfg, s_apszDescs[i][1], &iPortSlave, 2 * i + 1);
-        if (RT_FAILURE(rc))
-            return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
-                                       N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][1]);
-
-        char szName[24];
-        RTStrPrintf(szName, sizeof(szName), "EmulatedATA%d", i);
-        rc = ataControllerInit(pDevIns, pCtl,
-                               iPortMaster, pThis->ahciPort[iPortMaster].pDrvBase,
-                               iPortSlave, pThis->ahciPort[iPortSlave].pDrvBase,
-                               &cbSSMState, szName, &pThis->ahciPort[iPortMaster].Led,
-                               &pThis->ahciPort[iPortMaster].StatBytesRead,
-                               &pThis->ahciPort[iPortMaster].StatBytesWritten);
-        if (RT_FAILURE(rc))
-            return rc;
-
-        cbTotalBufferSize += cbSSMState;
-
-        rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase1, 8, (RTHCPTR)i,
-                                     ahciIOPortWrite1, ahciIOPortRead1, ahciIOPortWriteStr1, ahciIOPortReadStr1, "AHCI");
-        if (RT_FAILURE(rc))
-            return rc;
-
-        if (pThis->fR0Enabled)
-        {
-            rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase1, 8, (RTR0PTR)i,
-                                           "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI R0");
+    if (pThis->fBootable)
+    {
+        /*
+         * Setup IDE emulation.
+         * We only emulate the I/O ports but not bus master DMA.
+         * If the configuration values are not found the setup of the ports is as follows:
+         *     Primary Master:   Port 0
+         *     Primary Slave:    Port 1
+         *     Secondary Master: Port 2
+         *     Secondary Slave:  Port 3
+         */
+
+        /*
+         * Setup I/O ports for the PCI device.
+         */
+        pThis->aCts[0].irq          = 12;
+        pThis->aCts[0].IOPortBase1  = 0x1e8;
+        pThis->aCts[0].IOPortBase2  = 0x3e6;
+        pThis->aCts[1].irq          = 11;
+        pThis->aCts[1].IOPortBase1  = 0x168;
+        pThis->aCts[1].IOPortBase2  = 0x366;
+
+        for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
+        {
+            PAHCIATACONTROLLER pCtl = &pThis->aCts[i];
+            uint32_t iPortMaster, iPortSlave;
+            uint32_t cbSSMState = 0;
+            static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
+            {
+                { "PrimaryMaster", "PrimarySlave" },
+                { "SecondaryMaster", "SecondarySlave" }
+            };
+
+            rc = CFGMR3QueryU32Def(pCfg, s_apszDescs[i][0], &iPortMaster, 2 * i);
+            if (RT_FAILURE(rc))
+                return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
+                                           N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][0]);
+
+            rc = CFGMR3QueryU32Def(pCfg, s_apszDescs[i][1], &iPortSlave, 2 * i + 1);
+            if (RT_FAILURE(rc))
+                return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
+                                           N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][1]);
+
+            char szName[24];
+            RTStrPrintf(szName, sizeof(szName), "EmulatedATA%d", i);
+            rc = ataControllerInit(pDevIns, pCtl,
+                                   iPortMaster, pThis->ahciPort[iPortMaster].pDrvBase,
+                                   iPortSlave, pThis->ahciPort[iPortSlave].pDrvBase,
+                                   &cbSSMState, szName, &pThis->ahciPort[iPortMaster].Led,
+                                   &pThis->ahciPort[iPortMaster].StatBytesRead,
+                                   &pThis->ahciPort[iPortMaster].StatBytesWritten);
             if (RT_FAILURE(rc))
                 return rc;
-        }
-
-        if (pThis->fGCEnabled)
-        {
-            rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i,
-                                            "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI GC");
+
+            cbTotalBufferSize += cbSSMState;
+
+            rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase1, 8, (RTHCPTR)i,
+                                         ahciIOPortWrite1, ahciIOPortRead1, ahciIOPortWriteStr1, ahciIOPortReadStr1, "AHCI");
             if (RT_FAILURE(rc))
                 return rc;
-        }
-
-        rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase2, 1, (RTHCPTR)i,
-                                     ahciIOPortWrite2, ahciIOPortRead2, NULL, NULL, "AHCI");
-        if (RT_FAILURE(rc))
-            return rc;
-
-        if (pThis->fR0Enabled)
-        {
-            rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase2, 1, (RTR0PTR)i,
-                                            "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI R0");
+
+            if (pThis->fR0Enabled)
+            {
+                rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase1, 8, (RTR0PTR)i,
+                                               "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI R0");
+                if (RT_FAILURE(rc))
+                    return rc;
+            }
+
+            if (pThis->fGCEnabled)
+            {
+                rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i,
+                                                "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI GC");
+                if (RT_FAILURE(rc))
+                    return rc;
+            }
+
+            rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase2, 1, (RTHCPTR)i,
+                                         ahciIOPortWrite2, ahciIOPortRead2, NULL, NULL, "AHCI");
             if (RT_FAILURE(rc))
                 return rc;
-        }
-
-        if (pThis->fGCEnabled)
-        {
-            rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i,
-                                            "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI GC");
-            if (RT_FAILURE(rc))
-                return rc;
+
+            if (pThis->fR0Enabled)
+            {
+                rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase2, 1, (RTR0PTR)i,
+                                                "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI R0");
+                if (RT_FAILURE(rc))
+                    return rc;
+            }
+
+            if (pThis->fGCEnabled)
+            {
+                rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i,
+                                                "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI GC");
+                if (RT_FAILURE(rc))
+                    return rc;
+            }
         }
     }
Index: /trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
===================================================================
--- /trunk/src/VBox/Devices/Storage/DevBusLogic.cpp	(revision 34008)
+++ /trunk/src/VBox/Devices/Storage/DevBusLogic.cpp	(revision 34009)
@@ -2960,4 +2960,5 @@
     PBUSLOGIC  pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
     int        rc = VINF_SUCCESS;
+    bool       fBootable = true;
     PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
 
@@ -2967,5 +2968,6 @@
     if (!CFGMR3AreValuesValid(pCfg,
                               "GCEnabled\0"
-                              "R0Enabled\0"))
+                              "R0Enabled\0"
+                              "Bootable\0"))
         return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
                                 N_("BusLogic configuration error: unknown option specified"));
@@ -2982,5 +2984,9 @@
                                 N_("BusLogic configuration error: failed to read R0Enabled as boolean"));
     Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
-
+    rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("BusLogic configuration error: failed to read Bootable as boolean"));
+    Log(("%s: fBootable=%RTbool\n", __FUNCTION__, fBootable));
 
     pThis->pDevInsR3 = pDevIns;
@@ -3019,11 +3025,14 @@
         return rc;
 
-    /* Register I/O port space in ISA region for BIOS access. */
-    rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_ISA_IO_PORT, 3, NULL,
-                                 buslogicIsaIOPortWrite, buslogicIsaIOPortRead,
-                                 buslogicIsaIOPortWriteStr, buslogicIsaIOPortReadStr,
-                                 "BusLogic BIOS");
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register legacy I/O handlers"));
+    if (fBootable)
+    {
+        /* Register I/O port space in ISA region for BIOS access. */
+        rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_ISA_IO_PORT, 3, NULL,
+                                     buslogicIsaIOPortWrite, buslogicIsaIOPortRead,
+                                     buslogicIsaIOPortWriteStr, buslogicIsaIOPortReadStr,
+                                     "BusLogic BIOS");
+        if (RT_FAILURE(rc))
+            return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register legacy I/O handlers"));
+    }
 
     /* Initialize task cache. */
Index: /trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp
===================================================================
--- /trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp	(revision 34008)
+++ /trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp	(revision 34009)
@@ -4940,4 +4940,5 @@
     char *pszCtrlType = NULL;
     char  szDevTag[20], szTaggedText[64];
+    bool fBootable = true;
     PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
 
@@ -4950,5 +4951,6 @@
                                     "RequestQueueDepth\0"
                                     "ControllerType\0"
-                                    "NumPorts\0");
+                                    "NumPorts\0"
+                                    "Bootable\0");
     if (RT_FAILURE(rc))
         return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
@@ -4988,5 +4990,5 @@
                                 N_("LsiLogic configuration error: failed to read ControllerType as string"));
     Log(("%s: ControllerType=%s\n", __FUNCTION__, pszCtrlType));
-    
+
     rc = lsilogicGetCtrlTypeFromString(pThis, pszCtrlType);
     MMR3HeapFree(pszCtrlType);
@@ -5015,4 +5017,10 @@
         return PDMDEV_SET_ERROR(pDevIns, rc,
                                 N_("LsiLogic configuration error: failed to read NumPorts as integer"));
+
+    rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("LsiLogic configuration error: failed to read Bootable as boolean"));
+    Log(("%s: Bootable=%RTbool\n", __FUNCTION__, fBootable));
 
     /* Init static parts. */
@@ -5119,5 +5127,5 @@
      * Create critical sections protecting the reply post and free queues.
      */
-    RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%sRFQ", szDevTag);    
+    RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%sRFQ", szDevTag); 
     rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueCritSect, RT_SRC_POS,
                                szTaggedText);
@@ -5126,5 +5134,5 @@
                                 N_("LsiLogic: cannot create critical section for reply free queue"));
 
-    RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%sRPQ", szDevTag);        
+    RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%sRPQ", szDevTag);
     rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyPostQueueCritSect, RT_SRC_POS,
                                szTaggedText);
@@ -5210,6 +5218,9 @@
     AssertRC(rc);
 
-    /* Register I/O port space in ISA region for BIOS access, only for first controller. */
-    if (iInstance == 0)
+    /*
+     * Register I/O port space in ISA region for BIOS access
+     * if the controller is marked as bootable.
+     */
+    if (fBootable)
     {
         if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
@@ -5228,5 +5239,5 @@
         if (RT_FAILURE(rc))
             return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register legacy I/O handlers"));
-    }        
+    }
 
     /* Register save state handlers. */
Index: /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp
===================================================================
--- /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 34008)
+++ /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 34009)
@@ -1269,4 +1269,5 @@
     GEN_CHECK_OFF(AHCI, fR0Enabled);
     GEN_CHECK_OFF(AHCI, fSignalIdle);
+    GEN_CHECK_OFF(AHCI, fBootable);
     GEN_CHECK_OFF(AHCI, cPortsImpl);
     GEN_CHECK_OFF(AHCI, f8ByteMMIO4BytesWrittenSuccessfully);
