Changeset 34035 in vbox
- Timestamp:
- Nov 12, 2010 6:17:58 PM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/PC/DevACPI.cpp
r33540 r34035 511 511 }; 512 512 AssertCompileSize(ACPITBLISO, 10); 513 #define NUMBER_OF_IRQ_SOURCE_OVERRIDES 1513 #define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2 514 514 515 515 /** HPET Descriptor Structure */ … … 945 945 { 946 946 uint16_t cpus = s->cCpus; 947 AcpiTableMADT madt(cpus, 1 /* one source override */);947 AcpiTableMADT madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES); 948 948 949 949 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2); … … 976 976 977 977 /* Interrupt Source Overrides */ 978 /* Flags: 979 bits[3:2]: 980 00 conforms to the bus 981 01 edge-triggered 982 10 reserved 983 11 level-triggered 984 bits[1:0] 985 00 conforms to the bus 986 01 active-high 987 10 reserved 988 11 active-low */ 978 989 /* If changing, also update PDMIsaSetIrq() and MPS */ 979 990 ACPITBLISO* isos = madt.ISO_addr(); 991 /* Timer interrupt rule IRQ0 to GSI2 */ 980 992 isos[0].u8Type = 2; 981 993 isos[0].u8Length = sizeof(ACPITBLISO); … … 984 996 isos[0].u32GSI = 2; /* connected to pin 2 */ 985 997 isos[0].u16Flags = 0; /* conform to the bus */ 986 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 1); 998 999 /* ACPI interrupt rule - IRQ9 to GSI9 */ 1000 isos[1].u8Type = 2; 1001 isos[1].u8Length = sizeof(ACPITBLISO); 1002 isos[1].u8Bus = 0; /* Must be 0 */ 1003 isos[1].u8Source = 9; /* IRQ9 */ 1004 isos[1].u32GSI = 9; /* connected to pin 9 */ 1005 isos[1].u16Flags = 0xd; /* active high, level triggered */ 1006 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2); 987 1007 988 1008 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size()); … … 1077 1097 old_level = pm1a_level(s); 1078 1098 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0; 1099 1100 Log(("update_pm1a() old=%x new=%x\n", old_level, new_level)); 1079 1101 1080 1102 s->pm1a_en = en; … … 1150 1172 { 1151 1173 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface); 1174 Log(("acpiPowerButtonPress: handled=%d status=%x\n", s->fPowerButtonHandled, s->pm1a_sts)); 1152 1175 s->fPowerButtonHandled = false; 1153 1176 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en); … … 1777 1800 break; 1778 1801 default: 1802 AssertMsgFailed(("PM1 status read: width %d\n", cb)); 1779 1803 return VERR_IOM_IOPORT_UNUSED; 1780 1804 } … … 1790 1814 break; 1791 1815 default: 1816 AssertMsgFailed(("PM1 control read: width %d\n", cb)); 1792 1817 return VERR_IOM_IOPORT_UNUSED; 1793 1818 } … … 2384 2409 2385 2410 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, Address, cb)); 2411 2412 if (Address == 0x3c && u32Value == 0xff) 2413 { 2414 Log(("acpi: ignore bogus interrupt line settings\n")); 2415 return; 2416 } 2417 2386 2418 pThis->pfnAcpiPciConfigWrite(pPciDev, Address, u32Value, cb); 2387 2419 … … 2394 2426 int rc; 2395 2427 2396 RTIOPORT uNewBase = 2397 RTIOPORT(RT_LE2H_U32(*(uint32_t*)&pPciDev->config[0x40])); 2428 RTIOPORT uNewBase = RTIOPORT(PCIDevGetDWord(pPciDev, 0x40)); 2398 2429 uNewBase &= 0xffc0; 2399 2430
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