Changeset 34151 in vbox for trunk/src/VBox
- Timestamp:
- Nov 18, 2010 4:46:12 AM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
r34146 r34151 1022 1022 DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value) 1023 1023 { 1024 bool fOn = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))); 1025 int rc = VINF_SUCCESS; 1024 1026 if(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)) 1025 1027 { … … 1035 1037 HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST); 1036 1038 } 1037 /* @todo: use right offsets for right streams */ 1038 if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)) 1039 { 1040 Log(("hda: DMA(%x) switched on\n", offset)); 1041 if (offset == 0x80) 1042 AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(pState), 1); 1043 if (offset == 0x100) 1044 { 1039 switch (index) 1040 { 1041 case ICH6_HDA_REG_SD0CTL: 1042 AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(pState), fOn); 1043 Log(("hda: DMA SD0CTL switched %s\n", fOn ? "on" : " off")); 1044 break; 1045 case ICH6_HDA_REG_SD4CTL: 1045 1046 uint64_t u64BaseDMA = RT_MAKE_U64(SDBDPL(pState, 4), SDBDPU(pState, 4)); 1046 if (u64BaseDMA) 1047 AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(pState), 1); 1048 } 1049 } 1050 else 1051 { 1052 Log(("hda: DMA(%x) switched off\n", offset)); 1053 if (offset == 0x80) 1054 { 1055 AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(pState), 0); 1056 } 1057 if (offset == 0x100) 1058 { 1047 fOn = fOn && u64BaseDMA; 1059 1048 SDSTS(pState, 4) &= ~(1<<5); 1060 AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(pState), 0); 1061 } 1062 } 1063 int rc = hdaRegWriteU24(pState, offset, index, u32Value); 1049 AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(pState), fOn); 1050 Log(("hda: DMA SD4CTL switched %s\n", fOn ? "on" : " off")); 1051 break; 1052 default: 1053 Log(("Attempt to modify DMA state on unattached SDI(%s), ignored\n", s_ichIntelHDRegMap[index].abbrev)); 1054 break; 1055 } 1056 rc = hdaRegWriteU24(pState, offset, index, u32Value); 1064 1057 if (RT_FAILURE(rc)) 1065 1058 AssertRCReturn(rc, VINF_SUCCESS); … … 1293 1286 len = *(uint32_t *)&bdle[8]; 1294 1287 ioc = *(uint32_t *)&bdle[12]; 1295 Log(("hda: %s bdle[%d] a:%l x, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));1288 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1)); 1296 1289 sum += len; 1297 1290 } … … 1382 1375 } 1383 1376 1384 static uint32_t hdaWriteAudio(INTELHDLinkState *pState, uint32_t *pu32Avail, bool *fStop, uint32_t u32 LcblLimit)1377 static uint32_t hdaWriteAudio(INTELHDLinkState *pState, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit) 1385 1378 { 1386 1379 PHDABDLEDESC pBdle = &pState->stOutBdle; … … 1394 1387 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */ 1395 1388 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */ 1396 Log(("hda:wa: CVI( pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));1389 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen)); 1397 1390 /* border check assert */ 1398 1391 if ( ( !pBdle->u32BdleCviLen … … 1401 1394 { 1402 1395 /* buffer length is 0, to little data on marked as "under FIFOW" to send to backed.*/ 1403 Log(("hda:wa: exits CVI(iAvail:%d, cbUnderFifoW:%d, len:%d)\n", *pu32Avail, pBdle->u32BdleCviLen, pBdle->cbUnderFifoW));1396 Log(("hda:wa: exits CVI(iAvail:%d, cbUnderFifoW:%d, cvi:%d, len:%d)\n", *pu32Avail, pBdle->u32BdleCviLen, pBdle->u32BdleCvi, pBdle->cbUnderFifoW)); 1404 1397 *fStop = true; 1405 1398 return 0; … … 1411 1404 { 1412 1405 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */ 1413 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos; 1406 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos; /* align copy buffer to size of trailing space in BDLE buffer */ 1414 1407 cb2Copy = RT_MIN(cb2Copy, SDFIFOS(pState, 4) + 1 - pBdle->cbUnderFifoW); /* we may increase the counter in range of [0, FIFOS(pState, 4) + 1] */ 1415 cb2Copy = RT_MIN(cb2Copy, *pu32Avail); /* sanity check to avoid overriding sound backend buffer */1416 cb2Copy = RT_MIN(cb2Copy, u32 LcblLimit); /* avoid LCBL overrun */1408 cb2Copy = RT_MIN(cb2Copy, *pu32Avail); /* align copying buffer size up to size of back end buffer */ 1409 cb2Copy = RT_MIN(cb2Copy, u32CblLimit); /* avoid LCBL overrun */ 1417 1410 } 1418 1411 if ( cb2Copy == 0 … … 1432 1425 * Write to audio backend. 1433 1426 */ 1434 if (cb2Copy >= hdaFifoWToSz(pState, 4))1427 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, 4)) 1435 1428 { 1429 /* 1430 * We feed backend with new portion of fetched samples including not reported. 1431 */ 1436 1432 cbBackendCopy = AUD_write (OSD0FMT_TO_AUDIO_SELECTOR(pState), pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW); 1437 1433 Assert((cbBackendCopy)); … … 1444 1440 && pBdle->cbUnderFifoW <= cbBackendCopy) 1445 1441 Log(("hda:wa: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen)); 1446 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbBackendCopy); 1442 1443 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbBackendCopy); 1447 1444 pBdle->u32BdleCviPos += RT_MIN(cb2Copy, cbBackendCopy); 1448 1445 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32Avail >= cbBackendCopy)); /* sanity */ 1446 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */ 1449 1447 *pu32Avail -= cbBackendCopy; 1450 1448 cbTransfered += cbBackendCopy; … … 1487 1485 uint8_t u8Strm; 1488 1486 uint32_t *pu32Lpib; 1489 uint32_t u32 Lcbl;1487 uint32_t u32Cbl; 1490 1488 uint32_t u32Fifos; 1491 1489 uint32_t u32Fifow; … … 1499 1497 pu32Lpib = &SDLPIB(pState, 4); 1500 1498 pu32Sts = &SDSTS(pState, 4); 1501 u32 Lcbl = SDLCBL(pState, 4);1499 u32Cbl = SDLCBL(pState, 4); 1502 1500 pBdle = &pState->stOutBdle; 1503 1501 pBdle->u32BdleMaxCvi = SDLVI(pState, 4); … … 1512 1510 pu32Lpib = &SDLPIB(pState, 0); 1513 1511 pu32Sts = &SDSTS(pState, 0); 1514 u32 Lcbl = SDLCBL(pState, 0);1512 u32Cbl = SDLCBL(pState, 0); 1515 1513 u64BaseDMA = RT_MAKE_U64(SDBDPL(pState, 0), SDBDPU(pState, 0)); 1516 1514 pBdle = &pState->stInBdle; … … 1532 1530 while( avail && !fStop) 1533 1531 { 1534 Assert((avail >= 0 && (u32 Lcbl >= (*pu32Lpib)))); /* sanity */1535 uint32_t u32CblLimit = u32 Lcbl - (*pu32Lpib);1536 Log(("hda: CBL=%d, LPIB=%d\n", u32 Lcbl, *pu32Lpib));1532 Assert((avail >= 0 && (u32Cbl >= (*pu32Lpib)))); /* sanity */ 1533 uint32_t u32CblLimit = u32Cbl - (*pu32Lpib); 1534 Log(("hda: CBL=%d, LPIB=%d\n", u32Cbl, *pu32Lpib)); 1537 1535 switch (src) 1538 1536 { … … 1556 1554 { 1557 1555 *pu32Lpib += nBytes; 1558 /* 1559 * Update the buffer position and handle Cyclic Buffer Length (CBL) wraparound. 1556 1557 /* 1558 * Assert. Overlapping of buffer counter shouldn't happen. 1560 1559 */ 1561 Assert((*pu32Lpib <= u32 Lcbl));1560 Assert((*pu32Lpib <= u32Cbl)); 1562 1561 1563 1562 /* Optionally write back the current DMA position. */ … … 1569 1568 /* Process end of buffer condition. */ 1570 1569 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen 1571 || *pu32Lpib == u32 Lcbl)1570 || *pu32Lpib == u32Cbl) 1572 1571 { 1573 if (pBdle->fBdleCviIoc) 1572 if ( !pBdle->cbUnderFifoW 1573 && pBdle->fBdleCviIoc) 1574 1574 { 1575 1575 *pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS); 1576 1576 hdaProcessInterrupt(pState); 1577 *pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY); 1577 1578 } 1578 if (*pu32Lpib == u32 Lcbl)1579 *pu32Lpib -= u32 Lcbl;1579 if (*pu32Lpib == u32Cbl) 1580 *pu32Lpib -= u32Cbl; 1580 1581 1581 1582 if (pBdle->u32BdleCviPos == pBdle->u32BdleCviLen) … … 1584 1585 pBdle->u32BdleCvi++; 1585 1586 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1) 1586 {1587 1587 pBdle->u32BdleCvi = 0; 1588 } 1588 1589 1589 fetch_bd(pState, pBdle, u64BaseDMA); 1590 1590 }
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