Changeset 34201 in vbox
- Timestamp:
- Nov 19, 2010 2:22:31 PM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r34014 r34201 555 555 } 556 556 } else { 557 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",557 Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n", 558 558 R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq)); 559 559 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel); … … 1605 1605 1); 1606 1606 break; 1607 case 0x0800: 1608 /* PIC */ 1609 if (uVendor == 0x1014) 1610 { 1611 /* IBM */ 1612 if (uDevice == 0x0046 || uDevice == 0xFFFF) 1613 /* MPIC & MPIC2 */ 1614 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000); 1615 } 1616 break; 1617 case 0xff00: 1618 if ((uVendor == 0x0106b) 1619 && (uDevice == 0x0017 || uDevice == 0x0022)) 1620 { 1621 /* macio bridge */ 1622 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000); 1623 } 1624 break; 1625 case 0x0604: 1607 case 0x0604: 1626 1608 /* PCI-to-PCI bridge. */ 1627 1609 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1); … … 1677 1659 } 1678 1660 } 1679 1680 /* map the interrupt */ 1681 uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1); 1682 if (uPin != 0) 1683 { 1684 uint8_t uBridgeDevFn = uDevFn; 1685 uPin--; 1686 1687 /* We need to go up to the host bus to see which irq this device will assert there. */ 1688 while (cBridgeDepth != 0) 1689 { 1690 /* Get the pin the device would assert on the bridge. */ 1691 uPin = ((uBridgeDevFn >> 3) + uPin) & 3; 1692 uBridgeDevFn = paBridgePositions[cBridgeDepth]; 1693 cBridgeDepth--; 1694 } 1695 } 1696 } 1697 1698 static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 }; 1661 } 1699 1662 1700 1663 static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns) … … 1712 1675 pGlobals->uPciBiosMmio = UINT32_C(0xf0000000); 1713 1676 pGlobals->uBus = 0; 1714 1715 /*1716 * Activate IRQ mappings.1717 */1718 for (i = 0; i < 4; i++)1719 {1720 uint8_t irq = auPciIrqs[i];1721 /* Set to trigger level. */1722 elcr[irq >> 3] |= (1 << (irq & 7));1723 }1724 1725 /* Tell to the PIC. */1726 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));1727 if (rcStrict == VINF_SUCCESS)1728 rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));1729 if (rcStrict != VINF_SUCCESS)1730 {1731 AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));1732 return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);1733 }1734 1677 1735 1678 /*
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