Changeset 34299 in vbox

Timestamp:

Nov 23, 2010 4:52:34 PM (14 years ago)

Author:

vboxsync

Message:

PCI: fixed issue with bridge config space writes

File:

• trunk/src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (8 diffs)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -1626 +1626 @@
                 uint32_t u32Address = ich9pciGetRegionReg(iRegion);
 
-                /* Calculate size. */
+                /* Calculate size - we write all 1s into the BAR, and then evaluate which bits
+                   are cleared. . */
                 uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
                 ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
@@ -1739 +1740 @@
     int iRegionSize = pRegion->size;
 
+    Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
+         iRegion, iOffset, u8Val, iRegionSize));
+
     /* Region doesn't exist */
     if (iRegionSize == 0)
@@ -1746 +1750 @@
     /* Region size must be power of two */
     Assert((iRegionSize & (iRegionSize - 1)) == 0);
-    uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8)) & 0xff;
+    uint8_t uMask = (((uint32_t)iRegionSize - 1) >> (iOffset*8) ) & 0xff;
 
     if (iOffset == 0)
@@ -1753 +1757 @@
                 (1 << 2) - 1 /* 2 lowest bits for IO region */ :
                 (1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
-    }
-
-    u8Val = (PCIDevGetByte(aDev, uAddr) & uMask) | (u8Val & ~uMask);
+
+    }
+
+    uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
+    u8Val = (u8Old & uMask) | (u8Val & ~uMask);
+
+    Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
+
     PCIDevSetByte(aDev, uAddr, u8Val);
 }
@@ -1798 +1807 @@
     uint32_t addr = u32Address;
     bool fUpdateMappings = false;
+    bool fP2PBridge = false;
     for (uint32_t i = 0; i < len; i++)
     {
@@ -1829 +1839 @@
                 }
                 break;
-            default:
             case 0x01: /* PCI-PCI bridge */
+                fP2PBridge = true;
                 switch (addr)
                 {
@@ -1848 +1858 @@
                         fWritable = true;
                         break;
-            }
-            break;
+                }
+                break;
+            default:
+                AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
+                fWritable = false;
+                break;
         }
 
@@ -1886 +1900 @@
             case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
             {
-                int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
-                int iOffset = addr & 0x3;
-                ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
-                fUpdateMappings = true;
+                /* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
+                if (fP2PBridge)
+                    goto default_case;
+                else
+                {
+                    int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
+                    int iOffset = addr & 0x3;
+                    ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
+                    fUpdateMappings = true;
+                }
                 break;
             }
             default:
+            default_case:
                 if (fWritable)
                     PCIDevSetByte(aDev, addr, u8Val);