Changeset 35358 in vbox for trunk/src/VBox/Devices/Bus
- Timestamp:
- Dec 28, 2010 7:58:40 AM (14 years ago)
- svn:sync-xref-src-repo-rev:
- 69218
- Location:
- trunk/src/VBox/Devices/Bus
- Files:
-
- 3 edited
-
DevPciIch9.cpp (modified) (10 diffs)
-
DevPciRaw.cpp (modified) (12 diffs)
-
PCIInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r35357 r35358 296 296 { 297 297 int rc = VINF_SUCCESS; 298 299 if (pAddr->iRegister > 0xff) 300 { 301 LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, cb, val)); 302 goto out; 303 } 298 304 299 305 if (pAddr->iBus != 0) … … 927 933 static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM) 928 934 { 929 Assert(!PCIIsPassthrough(pPciDev));930 935 return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config)); 931 936 } … … 1180 1185 */ 1181 1186 uint8_t const fBridge = fIsBridge ? 2 : 1; 1182 Assert(!PCIIsPassthrough(pDev));1183 1187 uint8_t *pbDstConfig = &pDev->config[0]; 1184 1185 1188 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++) 1186 1189 if (s_aFields[i].fBridge & fBridge) … … 1376 1379 1377 1380 /* commit the loaded device config. */ 1378 Assert(!PCIIsPassthrough(pDev));1379 1381 pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */ 1380 1382 … … 1408 1410 static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM) 1409 1411 { 1410 Assert(!PCIIsPassthrough(pPciDev));1411 1412 return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config)); 1412 1413 } … … 1624 1625 1625 1626 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n")); 1626 #if 01627 /* We assign bridges starting from 16, to allow real PCI1628 device assignment into lower slots */1629 if (pGlobals->uBus == 0)1630 pGlobals->uBus = 16;1631 else1632 pGlobals->uBus++;1633 #else1634 1627 pGlobals->uBus++; 1635 #endif1636 1628 ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions); 1637 1629 break; … … 1743 1735 } 1744 1736 1745 AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),1746 0);1747 1748 1749 1737 if ( PCIIsMsiCapable(aDev) 1750 1738 && (u32Address >= aDev->Int.s.u8MsiCapOffset) … … 1763 1751 } 1764 1752 1753 AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"), 1754 0); 1765 1755 switch (len) 1766 1756 { … … 1818 1808 { 1819 1809 Assert(len <= 4); 1820 Assert(!PCIIsPassthrough(aDev));1821 1810 1822 1811 if ((u32Address + len) > 256 && (u32Address + len) < 4096) 1823 1812 { 1824 LogRel(("Write to extended registers falled back to the generic code: %s register %d len=%d\n", 1825 aDev->name, u32Address, len)); 1826 return; 1813 AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n")); 1827 1814 } 1828 1815 … … 2143 2130 if (pPciDev != NULL) 2144 2131 { 2145 if (PCIIsPassthrough(pPciDev))2146 {2147 printIndent(pHlp, iIndent);2148 /**2149 * For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,2150 * as host driver handles real devices interrupts.2151 */2152 pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %s%s - PASSTHROUGH\n",2153 pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,2154 pPciDev->name,2155 PCIIsMsiCapable(pPciDev) ? " MSI" : "",2156 PCIIsMsixCapable(pPciDev) ? " MSI-X" : ""2157 );2158 continue;2159 }2160 2161 2132 printIndent(pHlp, iIndent); 2162 2133 pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %04x-%04x%s%s", -
trunk/src/VBox/Devices/Bus/DevPciRaw.cpp
r35357 r35358 20 20 *******************************************************************************/ 21 21 #define LOG_GROUP LOG_GROUP_DEV_PCI 22 #include <VBox/vmm/pdmdev.h> 22 23 #include <VBox/log.h> 23 #define PCI_INCLUDE_PRIVATE24 #include <VBox/pci.h>25 #include <VBox/vmm/pdmdev.h>26 24 #include <VBox/vmm/stam.h> 27 #include <VBox/vmm/pdmpci.h>28 25 #include <iprt/assert.h> 29 26 #include <iprt/string.h> 30 #include <iprt/uuid.h>31 32 27 33 28 #include "VBoxDD.h" … … 43 38 *******************************************************************************/ 44 39 40 /* Temporary PDM stubs */ 41 typedef struct PDMPCIRAWREG 42 { 43 /** Struct version+magic number (PDM_PCIRAWREG_VERSION). */ 44 uint32_t u32Version; 45 46 } PDMPCIRAWREG; 47 /** Pointer to a raw PCI registration structure. */ 48 typedef PDMPCIRAWREG *PPDMPCIRAWREG; 49 50 /** Current PDMPCIRAWREG version number. */ 51 #define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0) 52 53 struct PDMPCIRAWHLPRC 54 { 55 uint32_t u32Version; 56 }; 57 typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC; 58 typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC; 59 60 struct PDMPCIRAWHLPR0 61 { 62 uint32_t u32Version; 63 }; 64 typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0; 65 typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0; 66 67 struct PDMPCIRAWHLPR3 68 { 69 uint32_t u32Version; 70 /** 71 * Gets the address of the RC PCI raw helpers. 72 * 73 * This should be called at both construction and relocation time 74 * to obtain the correct address of the RC helpers. 75 * 76 * @returns RC pointer to the PCI raw helpers. 77 * @param pDevIns Device instance of the raw PCI device. 78 */ 79 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns)); 80 81 /** 82 * Gets the address of the R0 PCI raw helpers. 83 * 84 * This should be called at both construction and relocation time 85 * to obtain the correct address of the R0 helpers. 86 * 87 * @returns R0 pointer to the PCI raw helpers. 88 * @param pDevIns Device instance of the raw PCI device. 89 */ 90 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns)); 91 92 /** Just a safety precaution. */ 93 uint32_t u32TheEnd; 94 }; 95 /** Pointer to raw PCI R3 helpers. */ 96 typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3; 97 /** Pointer to const raw PCI R3 helpers. */ 98 typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3; 99 100 /** 101 * @copydoc PDMDEVHLPR3::pfnPciRawRegister 102 */ 103 DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3) 104 { 105 //return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3); 106 return VINF_SUCCESS; 107 } 108 109 /* End of PDM stubs */ 110 45 111 typedef struct PciRawState 46 112 { … … 63 129 PCIDEVICE aPciDevice; 64 130 65 /* Device name, as provided by Main */66 char szDeviceName[64];67 131 /* Address of device on the host */ 68 int32_t i32HostDeviceAddress;132 PciBusAddress aHostDeviceAddress; 69 133 /* Address of device in the guest */ 70 int32_t i32GuestDeviceAddress;71 72 134 PciBusAddress aGuestDeviceAddress; 135 136 /* Global device lock */ 73 137 PDMCRITSECT csLock; 74 75 /**76 * Device port - LUN#0.77 *78 * @implements PDMIBASE79 * @implements PDMIPCIRAW80 */81 struct82 {83 /** The base interface for the PCI device port. */84 PDMIBASE IBase;85 /** The device port base interface. */86 PDMIPCIRAW IDevice;87 88 /** The base interface of the attached raw PCI driver. */89 R3PTRTYPE(PPDMIBASE) pDrvBase;90 /** The device interface of the attached raw PCI driver. */91 R3PTRTYPE(PPDMIPCIRAWCONNECTOR) pDrv;92 } Lun0;93 138 } PciRawState; 94 139 95 /** Pointer to the raw PCI instance data. */96 typedef PciRawState *PPciRawState;97 140 98 141 #ifndef VBOX_DEVICE_STRUCT_TESTCASE … … 107 150 RT_C_DECLS_END 108 151 152 /* 153 * Temporary control to disable locking if problems found 154 */ 109 155 DECLINLINE(int) pcirawLock(PciRawState* pThis, int rcBusy) 110 156 { … … 116 162 PDMCritSectLeave(&pThis->csLock); 117 163 } 164 118 165 119 166 PDMBOTHCBDECL(int) pcirawMMIORead(PPDMDEVINS pDevIns, … … 165 212 166 213 rc = pcirawLock(pThis, VINF_IOM_HC_MMIO_WRITE); 214 if (RT_UNLIKELY(rc != VINF_SUCCESS)) 167 215 return rc; 168 216 … … 283 331 } 284 332 285 static DECLCALLBACK(int) pcirawAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)286 {287 PciRawState *pThis = PDMINS_2_DATA(pDevIns, PciRawState *);288 289 LogFlow(("pcirawAttach: LUN%d\n", iLUN));290 /* Not yet used */291 return 0;292 }293 294 static DECLCALLBACK(void) pcirawDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)295 {296 PciRawState *pThis = PDMINS_2_DATA(pDevIns, PciRawState *);297 298 LogFlow(("pcirawDetach: LUN%d\n", iLUN));299 /* Not yet used */300 }301 302 303 333 /** 304 334 * Initialization routine. … … 307 337 * @param pDevIns The device instance data. 308 338 */ 309 static int pcirawInit(PPDMDEVINS pDevIns, PciBusAddress hostAddress , PciBusAddress guestAddress)339 static int pcirawInit(PPDMDEVINS pDevIns, PciBusAddress hostAddress) 310 340 { 311 341 unsigned i; … … 319 349 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 320 350 321 pThis->i32HostDeviceAddress = hostAddress.asLong(); 322 pThis->i32GuestDeviceAddress = guestAddress.asLong(); 351 pThis->aHostDeviceAddress.init(hostAddress); 323 352 324 353 pcirawReset(pDevIns); 325 354 326 355 return VINF_SUCCESS; 327 }328 329 330 static uint32_t pcirawConfigRead(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb)331 {332 PPDMDEVINS pDevIns = pPciDev->pDevIns;333 PciRawState* pThis = PDMINS_2_DATA(pDevIns, PciRawState *);334 335 Log2(("rawpci: PCI config read: 0x%x (%d)\n", Address, cb));336 337 return 0;338 }339 340 static void pcirawConfigWrite(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb)341 {342 PPDMDEVINS pDevIns = pPciDev->pDevIns;343 PciRawState *pThis = PDMINS_2_DATA(pDevIns, PciRawState *);344 345 Log2(("rawpci: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, Address, cb));346 }347 348 349 /**350 * @interface_method_impl{PDMIBASE,pfnQueryInterface}351 */352 static DECLCALLBACK(void *) pcirawQueryInterface(PPDMIBASE pInterface, const char *pszIID)353 {354 PciRawState* pThis = RT_FROM_CPP_MEMBER(pInterface, PciRawState, Lun0.IBase);355 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->Lun0.IBase);356 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIPCIRAW, &pThis->Lun0.IDevice);357 return NULL;358 }359 360 static DECLCALLBACK(int) pcirawFoo(PPDMIPCIRAW pInterface)361 {362 return 0;363 356 } 364 357 … … 380 373 "GCEnabled\0" 381 374 "R0Enabled\0" 382 "DeviceName\0"383 "GuestPCIBusNo\0"384 "GuestPCIDeviceNo\0"385 "GuestPCIFunctionNo\0"386 375 "HostPCIBusNo\0" 387 376 "HostPCIDeviceNo\0" … … 401 390 N_("Configuration error: failed to read R0Enabled as boolean")); 402 391 403 rc = CFGMR3QueryString(pCfg, "DeviceName", pThis->szDeviceName, sizeof(pThis->szDeviceName)); 392 /* Obtain host device address */ 393 uint32_t u32Bus, u32Device, u32Fn; 394 rc = CFGMR3QueryU32(pCfg, "HostPCIBusNo", &u32Bus); 404 395 if (RT_FAILURE(rc)) 405 396 return PDMDEV_SET_ERROR(pDevIns, rc, 406 N_("Configuration error: failed to read DeviceName as string")); 407 408 PciBusAddress hostAddress, guestAddress; 409 410 /* Obtain device address info */ 411 uint32_t u32Bus, u32Device, u32Fn; 412 413 do { 414 rc = CFGMR3QueryU32(pCfg, "HostPCIBusNo", &u32Bus); 415 if (RT_FAILURE(rc)) 397 N_("Configuration error: Querying \"HostPCIBusNo\" as a int failed")); 398 rc = CFGMR3QueryU32(pCfg, "HostPCIDeviceNo", &u32Device); 399 if (RT_FAILURE(rc)) 400 return PDMDEV_SET_ERROR(pDevIns, rc, 401 N_("Configuration error: Querying \"HostPCIDeviceNo\" as a int failed")); 402 rc = CFGMR3QueryU32(pCfg, "HostPCIFunctionNo", &u32Fn); 403 if (RT_FAILURE(rc)) 404 return PDMDEV_SET_ERROR(pDevIns, rc, 405 N_("Configuration error: Querying \"HostPCIFunctionNo\" as a int failed")); 406 407 408 /* Initialize the device state */ 409 rc = pcirawInit(pDevIns, PciBusAddress(u32Bus, u32Device, u32Fn)); 410 if (RT_FAILURE(rc)) 411 return rc; 412 413 pThis->pDevInsR3 = pDevIns; 414 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 415 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 416 417 /* 418 * Register the raw device and get helpers. 419 */ 420 PciRawReg.u32Version = PDM_PCIRAWREG_VERSION; 421 rc = PDMDevHlpPciRawRegister(pDevIns, &PciRawReg, &pThis->pPciRawHlpR3); 422 if (RT_FAILURE(rc)) 423 { 424 AssertMsgRC(rc, ("Cannot PciRawRegister: %Rrc\n", rc)); 425 return rc; 426 } 427 428 /* 429 * Initialize critical section. 430 */ 431 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csLock, RT_SRC_POS, "PCIRAW"); 432 if (RT_FAILURE(rc)) 433 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Raw PCI device cannot initialize critical section")); 434 435 #if 0 436 /* 437 * Register IO/MMIO ranges for guest, basing on real device ranges. 438 */ 439 for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++) 440 { 441 442 } 443 #endif 444 445 if (fRCEnabled) 446 { 447 pThis->pPciRawHlpRC = pThis->pPciRawHlpR3->pfnGetRCHelpers(pDevIns); 448 if (!pThis->pPciRawHlpRC) 416 449 { 417 PDMDEV_SET_ERROR(pDevIns, rc, 418 N_("Configuration error: Querying \"HostPCIBusNo\" as a int failed")); 419 break; 450 AssertReleaseMsgFailed(("cannot get RC helper\n")); 451 return VERR_INTERNAL_ERROR; 420 452 } 421 rc = CFGMR3QueryU32(pCfg, "HostPCIDeviceNo", &u32Device); 422 if (RT_FAILURE(rc)) 453 } 454 if (fR0Enabled) 455 { 456 pThis->pPciRawHlpR0 = pThis->pPciRawHlpR3->pfnGetR0Helpers(pDevIns); 457 if (!pThis->pPciRawHlpR0) 423 458 { 424 PDMDEV_SET_ERROR(pDevIns, rc, 425 N_("Configuration error: Querying \"HostPCIDeviceNo\" as a int failed")); 426 break; 459 AssertReleaseMsgFailed(("cannot get R0 helper\n")); 460 return VERR_INTERNAL_ERROR; 427 461 } 428 rc = CFGMR3QueryU32(pCfg, "HostPCIFunctionNo", &u32Fn); 429 if (RT_FAILURE(rc)) 430 { 431 PDMDEV_SET_ERROR(pDevIns, rc, 432 N_("Configuration error: Querying \"HostPCIFunctionNo\" as a int failed")); 433 break; 434 } 435 hostAddress = PciBusAddress(u32Bus, u32Device, u32Fn); 436 437 rc = CFGMR3QueryU32(pCfg, "GuestPCIBusNo", &u32Bus); 438 if (RT_FAILURE(rc)) 439 { 440 PDMDEV_SET_ERROR(pDevIns, rc, 441 N_("Configuration error: Querying \"GuestPCIBusNo\" as a int failed")); 442 break; 443 } 444 rc = CFGMR3QueryU32(pCfg, "GuestPCIDeviceNo", &u32Device); 445 if (RT_FAILURE(rc)) 446 { 447 PDMDEV_SET_ERROR(pDevIns, rc, 448 N_("Configuration error: Querying \"GuestPCIDeviceNo\" as a int failed")); 449 break; 450 } 451 rc = CFGMR3QueryU32(pCfg, "GuestPCIFunctionNo", &u32Fn); 452 if (RT_FAILURE(rc)) 453 { 454 PDMDEV_SET_ERROR(pDevIns, rc, 455 N_("Configuration error: Querying \"GuestPCIFunctionNo\" as a int failed")); 456 break; 457 } 458 guestAddress = PciBusAddress(u32Bus, u32Device, u32Fn); 459 460 /* Initialize the device state */ 461 rc = pcirawInit(pDevIns, hostAddress, guestAddress); 462 if (RT_FAILURE(rc)) 463 break; 464 465 pThis->pDevInsR3 = pDevIns; 466 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 467 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 468 469 /* 470 * Register the raw device and get helpers. 471 */ 472 PciRawReg.u32Version = PDM_PCIRAWREG_VERSION; 473 rc = PDMDevHlpPciRawRegister(pDevIns, &PciRawReg, &pThis->pPciRawHlpR3); 474 if (RT_FAILURE(rc)) 475 { 476 AssertMsgRC(rc, ("Cannot PciRawRegister: %Rrc\n", rc)); 477 break; 478 } 479 480 /* 481 * Initialize critical section. 482 */ 483 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csLock, RT_SRC_POS, "PCIRAW"); 484 if (RT_FAILURE(rc)) 485 { 486 PDMDEV_SET_ERROR(pDevIns, rc, N_("Raw PCI device cannot initialize critical section")); 487 break; 488 } 489 490 /* Mark device as passthrough */ 491 PCISetPassthrough(&pThis->aPciDevice); 492 493 /* IBase */ 494 pThis->Lun0.IBase.pfnQueryInterface = pcirawQueryInterface; 495 pThis->Lun0.IDevice.pfnFoo = pcirawFoo; 496 497 /* 498 * Attach to the Main driver. 499 */ 500 rc = pDevIns->pHlpR3->pfnDriverAttach(pDevIns, 0 /*iLun*/, &pThis->Lun0.IBase, &pThis->Lun0.pDrvBase, "Device Port"); 501 if (RT_FAILURE(rc)) 502 { 503 rc = PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("Raw PCI failed to attach Main driver")); 504 break; 505 } 506 507 pThis->Lun0.pDrv = PDMIBASE_QUERY_INTERFACE(pThis->Lun0.pDrvBase, PDMIPCIRAWCONNECTOR); 508 if (!pThis->Lun0.pDrv) 509 { 510 rc = PDMDevHlpVMSetError(pDevIns, VERR_PDM_MISSING_INTERFACE, RT_SRC_POS, N_("Raw PCI failed to query interface")); 511 break; 512 } 513 514 /* Just a safety measure, this data shall never be reached */ 515 PCIDevSetVendorId(&pThis->aPciDevice, 0xdead); 516 PCIDevSetDeviceId(&pThis->aPciDevice, 0xbeef); 517 518 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->aPciDevice); 519 if (RT_FAILURE(rc)) 520 break; 521 522 PDMDevHlpPCISetConfigCallbacks(pDevIns, &pThis->aPciDevice, 523 pcirawConfigRead, NULL /* we don't care about old ones */, 524 pcirawConfigWrite, NULL /* we don't care about old ones */); 525 526 #if 1 527 /* 528 * Register IO/MMIO ranges for the guest, basing on real device ranges. 529 */ 530 for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++) 531 { 532 RTHCPHYS RegStart; 533 uint64_t iRegSize; 534 bool fMmio; 535 536 if (pThis->Lun0.pDrv->pfnGetRegionInfo(pThis->Lun0.pDrv, hostAddress.asLong(), iRegion, 537 &RegStart, &iRegSize, &fMmio)) 538 { 539 /* If region is present, register callbacks in guest. 540 @todo: replace it with direct region access with remap */ 541 // @todo: check if host's PA make sense for the guest 542 if (fMmio) 543 { 544 rc = PDMDevHlpMMIORegister(pDevIns, RegStart, iRegSize, NULL, 545 pcirawMMIOWrite, pcirawMMIORead, NULL, 546 "Raw PCI MMIO regions"); 547 if (RT_FAILURE(rc)) 548 { 549 AssertMsgRC(rc, ("Cannot register MMIO: %Rrc\n", rc)); 550 break; 551 } 552 } 553 else 554 { 555 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)RegStart, iRegSize, NULL, 556 pcirawIOPortWrite, pcirawIOPortRead, NULL, NULL, 557 "Raw PCI IO regions"); 558 if (RT_FAILURE(rc)) 559 { 560 AssertMsgRC(rc, ("Cannot register IO: %Rrc\n", rc)); 561 break; 562 } 563 } 564 } 565 } 566 567 if (RT_FAILURE(rc)) 568 break; 569 #endif 570 571 if (fRCEnabled) 572 { 573 pThis->pPciRawHlpRC = pThis->pPciRawHlpR3->pfnGetRCHelpers(pDevIns); 574 if (!pThis->pPciRawHlpRC) 575 { 576 AssertReleaseMsgFailed(("cannot get RC helper\n")); 577 rc = VERR_INTERNAL_ERROR; 578 break; 579 } 580 } 581 if (fR0Enabled) 582 { 583 pThis->pPciRawHlpR0 = pThis->pPciRawHlpR3->pfnGetR0Helpers(pDevIns); 584 if (!pThis->pPciRawHlpR0) 585 { 586 AssertReleaseMsgFailed(("cannot get R0 helper\n")); 587 rc = VERR_INTERNAL_ERROR; 588 break; 589 } 590 } 591 592 /* Register SSM callbacks */ 593 rc = PDMDevHlpSSMRegister3(pDevIns, PCIRAW_SAVED_STATE_VERSION, sizeof(*pThis), pcirawLiveExec, pcirawSaveExec, pcirawLoadExec); 594 if (RT_FAILURE(rc)) 595 break; 596 } while (0); 597 /* Notify Main about result of PCI device attach attempt */ 598 if (pThis->Lun0.pDrv != NULL) 599 pThis->Lun0.pDrv->pfnPciDeviceConstructComplete(pThis->Lun0.pDrv, hostAddress.asLong(), guestAddress.asLong(), 600 rc, pThis->szDeviceName); 601 602 return rc; 462 } 463 464 /* Register SSM callbacks */ 465 rc = PDMDevHlpSSMRegister3(pDevIns, PCIRAW_SAVED_STATE_VERSION, sizeof(*pThis), pcirawLiveExec, pcirawSaveExec, pcirawLoadExec); 466 if (RT_FAILURE(rc)) 467 return rc; 468 469 return VINF_SUCCESS; 603 470 } 604 471 … … 644 511 NULL, 645 512 /* pfnAttach */ 646 NULL , //pcirawAttach,513 NULL, 647 514 /* pfnDetach */ 648 NULL, //pcirawDetach,515 NULL, 649 516 /* pfnQueryInterface. */ 650 517 NULL, -
trunk/src/VBox/Devices/Bus/PCIInternal.h
r35357 r35358 87 87 /** Flag whether the device is capable of MSI-X. 88 88 * This one is set by MsixInit(). */ 89 PCIDEV_FLAG_MSIX_CAPABLE = 1<<4, 90 /** Flag if device represents real physical device in passthrough mode. */ 91 PCIDEV_FLAG_PASSTHROUGH = 1<<5 89 PCIDEV_FLAG_MSIX_CAPABLE = 1<<4 92 90 }; 93 91
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