Changeset 36079 in vbox for trunk/include/VBox
- Timestamp:
- Feb 24, 2011 5:10:31 PM (14 years ago)
- Location:
- trunk/include/VBox
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/pci.h
r35738 r36079 547 547 DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t uOffset) 548 548 { 549 #ifdef PCIDEVICEINT_DECLARED 550 Assert((pPciDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) == 0); 551 #endif 549 552 return pPciDev->config[uOffset]; 550 553 } … … 557 560 DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t uOffset) 558 561 { 562 #ifdef PCIDEVICEINT_DECLARED 563 Assert((pPciDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) == 0); 564 #endif 559 565 uint16_t u16Value = *(uint16_t*)&pPciDev->config[uOffset]; 560 566 return RT_H2LE_U16(u16Value); … … 568 574 DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t uOffset) 569 575 { 576 #ifdef PCIDEVICEINT_DECLARED 577 Assert((pPciDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) == 0); 578 #endif 570 579 uint32_t u32Value = *(uint32_t*)&pPciDev->config[uOffset]; 571 580 return RT_H2LE_U32(u32Value); … … 579 588 DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t uOffset) 580 589 { 590 #ifdef PCIDEVICEINT_DECLARED 591 Assert((pPciDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) == 0); 592 #endif 581 593 uint64_t u64Value = *(uint64_t*)&pPciDev->config[uOffset]; 582 594 return RT_H2LE_U64(u64Value); … … 920 932 921 933 #ifdef PCIDEVICEINT_DECLARED 922 /** @todo r=bird: These are internal methods and should start with lowercase 923 * prefix as well as including the 'Dev' bit: s/PCI\(Set|Get\)/pciDev\1/ 924 * 925 * Also: s/uFlags/fFlags/ 926 */ 927 928 DECLINLINE(void) PCISetRequestedDevfunc(PPCIDEVICE pDev) 929 { 930 pDev->Int.s.uFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC; 931 } 932 933 DECLINLINE(void) PCIClearRequestedDevfunc(PPCIDEVICE pDev) 934 { 935 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC; 936 } 937 938 DECLINLINE(bool) PCIIsRequestedDevfunc(PPCIDEVICE pDev) 939 { 940 return (pDev->Int.s.uFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0; 941 } 942 943 DECLINLINE(void) PCISetPci2PciBridge(PPCIDEVICE pDev) 944 { 945 pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE; 946 } 947 948 DECLINLINE(bool) PCIIsPci2PciBridge(PPCIDEVICE pDev) 949 { 950 return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0; 951 } 952 953 DECLINLINE(void) PCISetPciExpress(PPCIDEVICE pDev) 954 { 955 pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE; 956 } 957 958 DECLINLINE(bool) PCIIsPciExpress(PPCIDEVICE pDev) 959 { 960 return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0; 961 } 962 963 DECLINLINE(void) PCISetMsiCapable(PPCIDEVICE pDev) 964 { 965 pDev->Int.s.uFlags |= PCIDEV_FLAG_MSI_CAPABLE; 966 } 967 968 DECLINLINE(void) PCIClearMsiCapable(PPCIDEVICE pDev) 969 { 970 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_MSI_CAPABLE; 971 } 972 973 DECLINLINE(bool) PCIIsMsiCapable(PPCIDEVICE pDev) 974 { 975 return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0; 976 } 977 978 DECLINLINE(void) PCISetMsixCapable(PPCIDEVICE pDev) 979 { 980 pDev->Int.s.uFlags |= PCIDEV_FLAG_MSIX_CAPABLE; 981 } 982 983 DECLINLINE(void) PCIClearMsixCapable(PPCIDEVICE pDev) 984 { 985 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE; 986 } 987 988 DECLINLINE(bool) PCIIsMsixCapable(PPCIDEVICE pDev) 989 { 990 return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0; 991 } 992 993 DECLINLINE(void) PCISetPassthrough(PPCIDEVICE pDev) 994 { 995 pDev->Int.s.uFlags |= PCIDEV_FLAG_PASSTHROUGH; 996 } 997 998 DECLINLINE(void) PCIClearPassthrough(PPCIDEVICE pDev) 999 { 1000 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_PASSTHROUGH; 1001 } 1002 1003 DECLINLINE(bool) PCIIsPassthrough(PPCIDEVICE pDev) 1004 { 1005 return (pDev->Int.s.uFlags & PCIDEV_FLAG_PASSTHROUGH) != 0; 934 DECLINLINE(void) pciDevSetRequestedDevfunc(PPCIDEVICE pDev) 935 { 936 pDev->Int.s.fFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC; 937 } 938 939 DECLINLINE(void) pciDevClearRequestedDevfunc(PPCIDEVICE pDev) 940 { 941 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC; 942 } 943 944 DECLINLINE(bool) pciDevIsRequestedDevfunc(PPCIDEVICE pDev) 945 { 946 return (pDev->Int.s.fFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0; 947 } 948 949 DECLINLINE(void) pciDevSetPci2PciBridge(PPCIDEVICE pDev) 950 { 951 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE; 952 } 953 954 DECLINLINE(bool) pciDevIsPci2PciBridge(PPCIDEVICE pDev) 955 { 956 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0; 957 } 958 959 DECLINLINE(void) pciDevSetPciExpress(PPCIDEVICE pDev) 960 { 961 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE; 962 } 963 964 DECLINLINE(bool) pciDevIsPciExpress(PPCIDEVICE pDev) 965 { 966 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0; 967 } 968 969 DECLINLINE(void) pciDevSetMsiCapable(PPCIDEVICE pDev) 970 { 971 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI_CAPABLE; 972 } 973 974 DECLINLINE(void) pciDevClearMsiCapable(PPCIDEVICE pDev) 975 { 976 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI_CAPABLE; 977 } 978 979 DECLINLINE(bool) pciDevIsMsiCapable(PPCIDEVICE pDev) 980 { 981 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0; 982 } 983 984 DECLINLINE(void) pciDevSetMsixCapable(PPCIDEVICE pDev) 985 { 986 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSIX_CAPABLE; 987 } 988 989 DECLINLINE(void) pciDevClearMsixCapable(PPCIDEVICE pDev) 990 { 991 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE; 992 } 993 994 DECLINLINE(bool) pciDevIsMsixCapable(PPCIDEVICE pDev) 995 { 996 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0; 997 } 998 999 DECLINLINE(void) pciDevSetPassthrough(PPCIDEVICE pDev) 1000 { 1001 pDev->Int.s.fFlags |= PCIDEV_FLAG_PASSTHROUGH; 1002 } 1003 1004 DECLINLINE(void) pciDevClearPassthrough(PPCIDEVICE pDev) 1005 { 1006 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_PASSTHROUGH; 1007 } 1008 1009 DECLINLINE(bool) pciDevIsPassthrough(PPCIDEVICE pDev) 1010 { 1011 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) != 0; 1006 1012 } 1007 1013 -
trunk/include/VBox/rawpci.h
r36055 r36079 87 87 uint64_t iRegionSize; 88 88 RTR3PTR pvAddressR3; 89 RTR0PTR pvAddressR0; 89 RTR0PTR pvAddressR0; 90 90 } PCIRAWREQUNMAPREGION; 91 91 … … 126 126 { 127 127 /* in */ 128 RT GCPHYSAddress;128 RTR0PTR Address; 129 129 PCIRAWMEMLOC Value; 130 130 } PCIRAWREQMMIOWRITE; … … 134 134 { 135 135 /* in */ 136 RT GCPHYSAddress;136 RTR0PTR Address; 137 137 /* inout (Value.cb is in) */ 138 138 PCIRAWMEMLOC Value; … … 296 296 RTHCPHYS RegionStart, 297 297 uint64_t u64RegionSize, 298 RTR0PTR *pRegionBase ));298 RTR0PTR *pRegionBaseR0)); 299 299 300 300 /**
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