Changeset 36254 in vbox for trunk/src/VBox

Timestamp:

Mar 10, 2011 5:22:08 PM (14 years ago)

Author:

vboxsync

Message:

GIP,++: Lots of CPUs (disabled).

Location:

trunk/src/VBox

Files:

• HostDrivers/Support/SUPDrv.c (modified) (23 diffs)
• HostDrivers/Support/freebsd/Makefile (modified) (1 diff)
• HostDrivers/Support/freebsd/files_vboxdrv (modified) (1 diff)
• HostDrivers/Support/linux/Makefile (modified) (1 diff)
• HostDrivers/Support/linux/files_vboxdrv (modified) (1 diff)
• Runtime/common/time/timesupA.mac (modified) (2 diffs)
• Runtime/common/time/timesupref.h (modified) (1 diff)
• Runtime/generic/RTMpGetArraySize-generic.cpp (modified) (2 diffs)
• VMM/VMMR3/TM.cpp (modified) (5 diffs)

trunk/src/VBox/HostDrivers/Support/SUPDrv.c

@@ -131 +131 @@
 static DECLCALLBACK(void)   supdrvGipAsyncTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick);
 static DECLCALLBACK(void)   supdrvGipMpEvent(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvUser);
-static void                 supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys, uint64_t u64NanoTS, unsigned uUpdateHz);
+static void                 supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys,
+                                          uint64_t u64NanoTS, unsigned uUpdateHz, unsigned cCpus);
+static DECLCALLBACK(void)   supdrvGipInitOnCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2);
 static void                 supdrvGipTerm(PSUPGLOBALINFOPAGE pGip);
-static void                 supdrvGipUpdate(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC, uint64_t iTick);
-static void                 supdrvGipUpdatePerCpu(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC, unsigned iCpu, uint64_t iTick);
+static void                 supdrvGipUpdate(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC, RTCPUID idCpu, uint64_t iTick);
+static void                 supdrvGipUpdatePerCpu(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC,
+                                                  RTCPUID idCpu, uint8_t idApic, uint64_t iTick);
 
 
@@ -289 +292 @@
     { "RTThreadUserWait",                       (void *)RTThreadUserWait },
     { "RTThreadUserWaitNoResume",               (void *)RTThreadUserWaitNoResume },
-#else 
-    /**  
-     * @todo: remove me, once above code enabled.  
-     * We need RTThreadCreate/RTThreadWait in the PCI driver. 
-     */ 
-    { "RTThreadCreate",                         (void *)RTThreadCreate }, 
-    { "RTThreadWait",                           (void *)RTThreadWait }, 
+#else
+    /**
+     * @todo: remove me, once above code enabled.
+     * We need RTThreadCreate/RTThreadWait in the PCI driver.
+     */
+    { "RTThreadCreate",                         (void *)RTThreadCreate },
+    { "RTThreadWait",                           (void *)RTThreadWait },
 #endif
     { "RTThreadPreemptIsEnabled",               (void *)RTThreadPreemptIsEnabled },
@@ -3213 +3216 @@
 {
     PSUPGLOBALINFOPAGE  pGip = (PSUPGLOBALINFOPAGE)pvUser1;
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    unsigned            iCpu = pGip->aiCpuFromApicId[ASMGetApicId()];
+#else
     unsigned            iCpu = ASMGetApicId();
-
+#endif
+
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    if (RT_LIKELY(iCpu < pGip->cCpus && pGip->aCPUs[iCpu].idCpu == idCpu))
+#else
     if (RT_LIKELY(iCpu < RT_ELEMENTS(pGip->aCPUs)))
+#endif
         supdrvGipReInitCpu(&pGip->aCPUs[iCpu], *(uint64_t *)pvUser2);
 
@@ -4807 +4818 @@
 static int supdrvGipCreate(PSUPDRVDEVEXT pDevExt)
 {
-    PSUPGLOBALINFOPAGE pGip;
-    RTHCPHYS HCPhysGip;
-    uint32_t u32SystemResolution;
-    uint32_t u32Interval;
-    int rc;
+    PSUPGLOBALINFOPAGE  pGip;
+    RTHCPHYS            HCPhysGip;
+    uint32_t            u32SystemResolution;
+    uint32_t            u32Interval;
+    unsigned            cCpus;
+    int                 rc;
+
 
     LogFlow(("supdrvGipCreate:\n"));
@@ -4821 +4834 @@
 
     /*
-     * Allocate a suitable page with a default kernel mapping.
-     */
-    rc = RTR0MemObjAllocLow(&pDevExt->GipMemObj, PAGE_SIZE, false);
+     * Check the CPU count.
+     */
+    cCpus = RTMpGetArraySize();
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    if (   cCpus > RTCPUSET_MAX_CPUS
+        || cCpus > 256 /*uint8_t is used for the mappings*/)
+#else
+    if (cCpus > RT_ELEMENTS(pGip->aCPUs))
+#endif
+    {
+#ifdef SUP_WITH_LOTS_OF_CPUS
+        SUPR0Printf("VBoxDrv: Too many CPUs (%u) for the GIP (max %u)\n", cCpus, RT_MIN(RTCPUSET_MAX_CPUS, 256));
+#else
+        SUPR0Printf("VBoxDrv: Too many CPUs (%u) for the GIP (max %u)\n", cCpus, RT_MIN(RT_ELEMENTS(pGip->aCPUs), 256));
+#endif
+        return VERR_TOO_MANY_CPUS;
+    }
+
+    /*
+     * Allocate a contiguous set of pages with a default kernel mapping.
+     */
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    rc = RTR0MemObjAllocCont(&pDevExt->GipMemObj, RT_UOFFSETOF(SUPGLOBALINFOPAGE, aCPUs[cCpus]), false /*fExecutable*/);
+#else
+    cCpus = RT_ELEMENTS(pGip->aCPUs);
+    rc = RTR0MemObjAllocLow(&pDevExt->GipMemObj, PAGE_SIZE, false /*fExecutable*/);
+#endif
     if (RT_FAILURE(rc))
     {
@@ -4839 +4876 @@
         u32Interval += u32SystemResolution;
 
-    supdrvGipInit(pDevExt, pGip, HCPhysGip, RTTimeSystemNanoTS(), 1000000000 / u32Interval /*=Hz*/);
+    supdrvGipInit(pDevExt, pGip, HCPhysGip, RTTimeSystemNanoTS(), 1000000000 / u32Interval /*=Hz*/, cCpus);
 
     /*
@@ -4858 +4895 @@
     if (RT_SUCCESS(rc))
     {
-        if (pGip->u32Mode == SUPGIPMODE_ASYNC_TSC)
-            rc = RTMpNotificationRegister(supdrvGipMpEvent, pDevExt);
+        rc = RTMpNotificationRegister(supdrvGipMpEvent, pDevExt);
         if (RT_SUCCESS(rc))
         {
-            /*
-             * We're good.
-             */
-            Log(("supdrvGipCreate: %ld ns interval.\n", (long)u32Interval));
-            g_pSUPGlobalInfoPage = pGip;
-            return VINF_SUCCESS;
-        }
-
-        OSDBGPRINT(("supdrvGipCreate: failed register MP event notfication. rc=%d\n", rc));
+            rc = RTMpOnAll(supdrvGipInitOnCpu, pDevExt, pGip);
+            if (RT_SUCCESS(rc))
+            {
+                /*
+                 * We're good.
+                 */
+                Log(("supdrvGipCreate: %u ns interval.\n", u32Interval));
+                g_pSUPGlobalInfoPage = pGip;
+                return VINF_SUCCESS;
+            }
+
+            OSDBGPRINT(("supdrvGipCreate: RTMpOnAll failed with rc=%Rrc\n", rc));
+            RTMpNotificationDeregister(supdrvGipMpEvent, pDevExt);
+
+        }
+        else
+            OSDBGPRINT(("supdrvGipCreate: failed to register MP event notfication. rc=%Rrc\n", rc));
     }
     else
     {
-        OSDBGPRINT(("supdrvGipCreate: failed create GIP timer at %ld ns interval. rc=%d\n", (long)u32Interval, rc));
+        OSDBGPRINT(("supdrvGipCreate: failed create GIP timer at %u ns interval. rc=%Rrc\n", u32Interval, rc));
         Assert(!pDevExt->pGipTimer);
     }
@@ -4945 +4989 @@
     uint64_t        NanoTS    = RTTimeSystemNanoTS();
 
-    supdrvGipUpdate(pDevExt->pGip, NanoTS, u64TSC, iTick);
+    supdrvGipUpdate(pDevExt->pGip, NanoTS, u64TSC, NIL_RTCPUID, iTick);
 
     ASMSetFlags(fOldFlags);
@@ -4966 +5010 @@
     /** @todo reset the transaction number and whatnot when iTick == 1. */
     if (pDevExt->idGipMaster == idCpu)
-        supdrvGipUpdate(pDevExt->pGip, NanoTS, u64TSC, iTick);
+        supdrvGipUpdate(pDevExt->pGip, NanoTS, u64TSC, idCpu, iTick);
     else
-        supdrvGipUpdatePerCpu(pDevExt->pGip, NanoTS, u64TSC, ASMGetApicId(), iTick);
+        supdrvGipUpdatePerCpu(pDevExt->pGip, NanoTS, u64TSC, idCpu, ASMGetApicId(), iTick);
 
     ASMSetFlags(fOldFlags);
@@ -4975 +5019 @@
 
 /**
+ * The calling CPU should be accounted as online, update GIP accordingly.
+ *
+ * This is used by supdrvGipMpEvent as well as the supdrvGipCreate.
+ *
+ * @param   pGip                The GIP.
+ * @param   idCpu               The CPU ID.
+ */
+static void supdrvGipMpEventOnline(PSUPGLOBALINFOPAGE pGip, RTCPUID idCpu)
+{
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    int         iCpuSet;
+    uint8_t     idApic;
+    uint32_t    i;
+
+    Assert(idCpu == RTMpCpuId());
+    Assert(pGip->cPossibleCpus == RTMpGetCount());
+
+    /*
+     * Update the globals.
+     */
+    ASMAtomicWriteU32(&pGip->cPresentCpus,  RTMpGetPresentCount());
+    ASMAtomicWriteU32(&pGip->cOnlineCpus,   RTMpGetOnlineCount());
+    iCpuSet = RTMpCpuIdToSetIndex(idCpu);
+    if (iCpuSet >= 0)
+    {
+        Assert(RTCpuSetIsMemberByIndex(&pGip->PossibleCpuSet, iCpuSet));
+        RTCpuSetAddByIndex(&pGip->OnlineCpuSet, iCpuSet);
+        RTCpuSetAddByIndex(&pGip->PresentCpuSet, iCpuSet);
+    }
+
+    /*
+     * Find our entry, or allocate one if not found.
+     * ASSUMES that CPU IDs are constant.
+     */
+    for (i = 0; i < pGip->cCpus; i++)
+        if (pGip->aCPUs[i].idCpu == idCpu)
+            break;
+
+    if (i >= pGip->cCpus)
+        for (i = 0; i < pGip->cCpus; i++)
+        {
+            bool fRc;
+            ASMAtomicCmpXchgSize(&pGip->aCPUs[i].idCpu, idCpu, NIL_RTCPUID, fRc);
+            if (fRc)
+                break;
+        }
+
+    AssertReturnVoid(i < pGip->cCpus);
+
+    /*
+     * Update the entry.
+     */
+    idApic = ASMGetApicId();
+    ASMAtomicUoWriteU16(&pGip->aCPUs[i].idApic,  idApic);
+    ASMAtomicUoWriteS16(&pGip->aCPUs[i].iCpuSet, (int16_t)iCpuSet);
+    ASMAtomicUoWriteSize(&pGip->aCPUs[i].idCpu,  idCpu);
+    ASMAtomicWriteSize(&pGip->aCPUs[i].enmState, SUPGIPCPUSTATE_ONLINE);
+
+    /*
+     * Update the APIC ID and CPU set index mappings.
+     */
+    ASMAtomicWriteU16(&pGip->aiCpuFromApicId[idApic],     i);
+    ASMAtomicWriteU16(&pGip->aiCpuFromCpuSetIdx[iCpuSet], i);
+#endif
+}
+
+
+/**
+ * The CPU should be accounted as offline, update the GIP accordingly.
+ *
+ * This is used by supdrvGipMpEvent.
+ *
+ * @param   pGip                The GIP.
+ * @param   idCpu               The CPU ID.
+ */
+static void supdrvGipMpEventOffline(PSUPGLOBALINFOPAGE pGip, RTCPUID idCpu)
+{
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    int         iCpuSet;
+    unsigned    i;
+
+    iCpuSet = RTMpCpuIdToSetIndex(idCpu);
+    AssertReturnVoid(iCpuSet >= 0);
+
+    i = pGip->aiCpuFromCpuSetIdx[iCpuSet];
+    AssertReturnVoid(i < pGip->cCpus);
+    AssertReturnVoid(pGip->aCPUs[i].idCpu == idCpu);
+
+    Assert(RTCpuSetIsMemberByIndex(&pGip->PossibleCpuSet, iCpuSet));
+    ASMAtomicWriteSize(&pGip->aCPUs[i].enmState, SUPGIPCPUSTATE_OFFLINE);
+    RTCpuSetDelByIndex(&pGip->OnlineCpuSet, iCpuSet);
+#endif
+}
+
+
+/**
  * Multiprocessor event notification callback.
  *
- * This is used to make sue that the GIP master gets passed on to
- * another CPU.
+ * This is used to make sure that the GIP master gets passed on to
+ * another CPU.  It also updates the associated CPU data.
  *
  * @param   enmEvent    The event.
@@ -4986 +5126 @@
 static DECLCALLBACK(void) supdrvGipMpEvent(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvUser)
 {
-    PSUPDRVDEVEXT   pDevExt = (PSUPDRVDEVEXT)pvUser;
+    PSUPDRVDEVEXT       pDevExt = (PSUPDRVDEVEXT)pvUser;
+    PSUPGLOBALINFOPAGE  pGip    = pDevExt->pGip;
+
+    /*
+     * Update the GIP CPU data.
+     */
+    if (pGip)
+    {
+        switch (enmEvent)
+        {
+            case RTMPEVENT_ONLINE:
+                supdrvGipMpEventOnline(pGip, idCpu);
+                break;
+            case RTMPEVENT_OFFLINE:
+                supdrvGipMpEventOffline(pGip, idCpu);
+                break;
+
+        }
+    }
+
+    /*
+     * Make sure there is a master GIP.
+     */
     if (enmEvent == RTMPEVENT_OFFLINE)
     {
@@ -5184 +5346 @@
  * @param   u64NanoTS   The current nanosecond timestamp.
  * @param   uUpdateHz   The update frequency.
- */
-static void supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys, uint64_t u64NanoTS, unsigned uUpdateHz)
-{
-    unsigned i;
+ * @param   cCpus       The CPU count.
+ */
+static void supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys,
+                          uint64_t u64NanoTS, unsigned uUpdateHz, unsigned cCpus)
+{
+    size_t const    cbGip = RT_ALIGN_Z(RT_OFFSETOF(SUPGLOBALINFOPAGE, aCPUs[cCpus]), PAGE_SIZE);
+    unsigned        i;
 #ifdef DEBUG_DARWIN_GIP
-    OSDBGPRINT(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz));
+    OSDBGPRINT(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d cCpus=%u\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz, cCpus));
 #else
-    LogFlow(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz));
+    LogFlow(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d cCpus=%u\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz, cCpus));
 #endif
 
@@ -5197 +5362 @@
      * Initialize the structure.
      */
-    memset(pGip, 0, PAGE_SIZE);
-    pGip->u32Magic          = SUPGLOBALINFOPAGE_MAGIC;
-    pGip->u32Version        = SUPGLOBALINFOPAGE_VERSION;
-    pGip->u32Mode           = supdrvGipDeterminTscMode(pDevExt);
-    pGip->u32UpdateHz       = uUpdateHz;
-    pGip->u32UpdateIntervalNS = 1000000000 / uUpdateHz;
+    memset(pGip, 0, cbGip);
+    pGip->u32Magic              = SUPGLOBALINFOPAGE_MAGIC;
+    pGip->u32Version            = SUPGLOBALINFOPAGE_VERSION;
+    pGip->u32Mode               = supdrvGipDeterminTscMode(pDevExt);
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    pGip->cCpus                 = (uint16_t)cCpus;
+    pGip->cPages                = (uint16_t)(cbGip / PAGE_SIZE);
+#endif
+    pGip->u32UpdateHz           = uUpdateHz;
+    pGip->u32UpdateIntervalNS   = 1000000000 / uUpdateHz;
     pGip->u64NanoTSLastUpdateHz = u64NanoTS;
-
-    for (i = 0; i < RT_ELEMENTS(pGip->aCPUs); i++)
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    RTCpuSetEmpty(&pGip->OnlineCpuSet);
+    pGip->cOnlineCpus           = RTMpGetOnlineCount();
+    pGip->cPresentCpus          = RTMpGetPresentCount();
+    RTCpuSetEmpty(&pGip->PresentCpuSet);
+    RTMpGetSet(&pGip->PossibleCpuSet);
+    pGip->cPossibleCpus         = RTMpGetCount();
+    pGip->idCpuMax              = RTMpGetMaxCpuId();
+    for (i = 0; i < RT_ELEMENTS(pGip->aiCpuFromApicId); i++)
+        pGip->aiCpuFromApicId[i]    = 0;
+    for (i = 0; i < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx); i++)
+        pGip->aiCpuFromCpuSetIdx[i] = UINT16_MAX;
+#endif
+
+    for (i = 0; i < cCpus; i++)
     {
         pGip->aCPUs[i].u32TransactionId  = 2;
         pGip->aCPUs[i].u64NanoTS         = u64NanoTS;
         pGip->aCPUs[i].u64TSC            = ASMReadTSC();
+
+#ifdef SUP_WITH_LOTS_OF_CPUS
+        pGip->aCPUs[i].enmState          = SUPGIPCPUSTATE_INVALID;
+        pGip->aCPUs[i].idCpu             = NIL_RTCPUID;
+        pGip->aCPUs[i].iCpuSet           = -1;
+        pGip->aCPUs[i].idApic            = UINT8_MAX;
+#endif
 
         /*
@@ -5232 +5421 @@
      * Link it to the device extension.
      */
-    pDevExt->pGip = pGip;
+    pDevExt->pGip      = pGip;
     pDevExt->HCPhysGip = HCPhys;
     pDevExt->cGipUsers = 0;
+}
+
+
+/**
+ * On CPU initialization callback for RTMpOnAll.
+ *
+ * @param   idCpu               The CPU ID.
+ * @param   pvUser1             The device extension.
+ * @param   pvUser2             The GIP.
+ */
+static DECLCALLBACK(void) supdrvGipInitOnCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2)
+{
+    /* This is good enough, even though it will update some of the globals a
+       bit to much. */
+    supdrvGipMpEventOnline((PSUPGLOBALINFOPAGE)pvUser2, idCpu);
 }
 
@@ -5281 +5485 @@
      * Update the NanoTS.
      */
-    ASMAtomicXchgU64(&pGipCpu->u64NanoTS, u64NanoTS);
+    ASMAtomicWriteU64(&pGipCpu->u64NanoTS, u64NanoTS);
 
     /*
@@ -5288 +5492 @@
     /** @todo validate the NanoTS delta, don't trust the OS to call us when it should... */
     u64TSCDelta = u64TSC - pGipCpu->u64TSC;
-    ASMAtomicXchgU64(&pGipCpu->u64TSC, u64TSC);
+    ASMAtomicWriteU64(&pGipCpu->u64TSC, u64TSC);
 
     if (u64TSCDelta >> 32)
@@ -5318 +5522 @@
     Assert(RT_ELEMENTS(pGipCpu->au32TSCHistory) == 8);
     iTSCHistoryHead = (pGipCpu->iTSCHistoryHead + 1) & 7;
-    ASMAtomicXchgU32(&pGipCpu->iTSCHistoryHead, iTSCHistoryHead);
-    ASMAtomicXchgU32(&pGipCpu->au32TSCHistory[iTSCHistoryHead], (uint32_t)u64TSCDelta);
+    ASMAtomicWriteU32(&pGipCpu->iTSCHistoryHead, iTSCHistoryHead);
+    ASMAtomicWriteU32(&pGipCpu->au32TSCHistory[iTSCHistoryHead], (uint32_t)u64TSCDelta);
 
     /*
@@ -5359 +5563 @@
         u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 6;
     }
-    ASMAtomicXchgU32(&pGipCpu->u32UpdateIntervalTSC, u32UpdateIntervalTSC + u32UpdateIntervalTSCSlack);
+    ASMAtomicWriteU32(&pGipCpu->u32UpdateIntervalTSC, u32UpdateIntervalTSC + u32UpdateIntervalTSCSlack);
 
     /*
@@ -5365 +5569 @@
      */
     u64CpuHz = ASMMult2xU32RetU64(u32UpdateIntervalTSC, pGip->u32UpdateHz);
-    ASMAtomicXchgU64(&pGipCpu->u64CpuHz, u64CpuHz);
+    ASMAtomicWriteU64(&pGipCpu->u64CpuHz, u64CpuHz);
 }
 
@@ -5375 +5579 @@
  * @param   u64NanoTS       The current nanosecond timesamp.
  * @param   u64TSC          The current TSC timesamp.
+ * @param   idCpu           The CPU ID.
  * @param   iTick           The current timer tick.
  */
-static void supdrvGipUpdate(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC, uint64_t iTick)
+static void supdrvGipUpdate(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC, RTCPUID idCpu, uint64_t iTick)
 {
     /*
@@ -5387 +5592 @@
     else
     {
+#ifdef SUP_WITH_LOTS_OF_CPUS
+        unsigned iCpu = pGip->aiCpuFromApicId[ASMGetApicId()];
+        if (RT_UNLIKELY(iCpu >= pGip->cCpus))
+            return;
+        pGipCpu = &pGip->aCPUs[iCpu];
+        if (RT_UNLIKELY(pGipCpu->idCpu != idCpu))
+            return;
+#else
         unsigned iCpu = ASMGetApicId();
         if (RT_UNLIKELY(iCpu >= RT_ELEMENTS(pGip->aCPUs)))
             return;
         pGipCpu = &pGip->aCPUs[iCpu];
+#endif
     }
 
@@ -5417 +5631 @@
             if (u32UpdateHz <= 2000 && u32UpdateHz >= 30)
             {
-                ASMAtomicXchgU32(&pGip->u32UpdateHz, u32UpdateHz);
-                ASMAtomicXchgU32(&pGip->u32UpdateIntervalNS, 1000000000 / u32UpdateHz);
+                ASMAtomicWriteU32(&pGip->u32UpdateHz, u32UpdateHz);
+                ASMAtomicWriteU32(&pGip->u32UpdateIntervalNS, 1000000000 / u32UpdateHz);
             }
 #endif
         }
-        ASMAtomicXchgU64(&pGip->u64NanoTSLastUpdateHz, u64NanoTS);
+        ASMAtomicWriteU64(&pGip->u64NanoTSLastUpdateHz, u64NanoTS);
     }
 
@@ -5443 +5657 @@
  * @param   u64NanoTS       The current nanosecond timesamp.
  * @param   u64TSC          The current TSC timesamp.
- * @param   iCpu            The CPU index.
+ * @param   idCpu           The CPU ID.
+ * @param   idApic          The APIC id for the CPU index.
  * @param   iTick           The current timer tick.
  */
-static void supdrvGipUpdatePerCpu(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC, unsigned iCpu, uint64_t iTick)
-{
-    PSUPGIPCPU  pGipCpu;
+static void supdrvGipUpdatePerCpu(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC,
+                                  RTCPUID idCpu, uint8_t idApic, uint64_t iTick)
+{
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    unsigned iCpu = pGip->aiCpuFromApicId[idApic];
+
+    if (RT_LIKELY(iCpu < pGip->cCpus))
+#else
+    unsigned iCpu = idApic;
 
     if (RT_LIKELY(iCpu < RT_ELEMENTS(pGip->aCPUs)))
-    {
-        pGipCpu = &pGip->aCPUs[iCpu];
-
-        /*
-         * Start update transaction.
-         */
-        if (!(ASMAtomicIncU32(&pGipCpu->u32TransactionId) & 1))
-        {
-            AssertMsgFailed(("Invalid transaction id, %#x, not odd!\n", pGipCpu->u32TransactionId));
+#endif
+    {
+        PSUPGIPCPU pGipCpu = &pGip->aCPUs[iCpu];
+#ifdef SUP_WITH_LOTS_OF_CPUS
+        if (pGipCpu->idCpu == idCpu)
+#endif
+        {
+
+            /*
+             * Start update transaction.
+             */
+            if (!(ASMAtomicIncU32(&pGipCpu->u32TransactionId) & 1))
+            {
+                AssertMsgFailed(("Invalid transaction id, %#x, not odd!\n", pGipCpu->u32TransactionId));
+                ASMAtomicIncU32(&pGipCpu->u32TransactionId);
+                pGipCpu->cErrors++;
+                return;
+            }
+
+            /*
+             * Update the data.
+             */
+            supdrvGipDoUpdateCpu(pGip, pGipCpu, u64NanoTS, u64TSC, iTick);
+
+            /*
+             * Complete transaction.
+             */
             ASMAtomicIncU32(&pGipCpu->u32TransactionId);
-            pGipCpu->cErrors++;
-            return;
-        }
-
-        /*
-         * Update the data.
-         */
-        supdrvGipDoUpdateCpu(pGip, pGipCpu, u64NanoTS, u64TSC, iTick);
-
-        /*
-         * Complete transaction.
-         */
-        ASMAtomicIncU32(&pGipCpu->u32TransactionId);
-    }
-}
+        }
+    }
+}

trunk/src/VBox/HostDrivers/Support/freebsd/Makefile

@@ -133 +133 @@
         RTSemEventMultiWaitNoResume-2-ex-generic.c \
         RTTimerCreate-generic.c \
-        timer-generic.c \
-        mppresent-generic.c
+        mppresent-generic.c \
+        timer-generic.c
 
 .PATH:  ${.CURDIR}/r0drv

trunk/src/VBox/HostDrivers/Support/freebsd/files_vboxdrv

@@ -158 +158 @@
     ${PATH_ROOT}/src/VBox/Runtime/generic/RTTimerCreate-generic.cpp=>generic/RTTimerCreate-generic.c \
     ${PATH_ROOT}/src/VBox/Runtime/generic/RTMpGetArraySize-generic.cpp=>generic/RTMpGetArraySize-generic.c \
+    ${PATH_ROOT}/src/VBox/Runtime/generic/mppresent-generic.cpp=>generic/mppresent-generic.c \
     ${PATH_ROOT}/src/VBox/Runtime/generic/timer-generic.cpp=>generic/timer-generic.c \
-    ${PATH_ROOT}/src/VBox/Runtime/generic/mppresent-generic.cpp=>generic/mppresent-generic.c \
     ${PATH_ROOT}/src/VBox/Runtime/r0drv/alloc-r0drv.cpp=>r0drv/alloc-r0drv.c \
     ${PATH_ROOT}/src/VBox/Runtime/r0drv/alloc-r0drv.h=>r0drv/alloc-r0drv.h \

trunk/src/VBox/HostDrivers/Support/linux/Makefile

@@ -138 +138 @@
         generic/RTSemEventMultiWaitNoResume-2-ex-generic.o \
         generic/RTTimerCreate-generic.o \
+        generic/mppresent-generic.o \
         generic/uuid-generic.o \
         VBox/log-vbox.o

trunk/src/VBox/HostDrivers/Support/linux/files_vboxdrv

@@ -146 +146 @@
     ${PATH_ROOT}/src/VBox/Runtime/generic/RTSemEventMultiWaitNoResume-2-ex-generic.cpp=>generic/RTSemEventMultiWaitNoResume-2-ex-generic.c \
     ${PATH_ROOT}/src/VBox/Runtime/generic/RTTimerCreate-generic.cpp=>generic/RTTimerCreate-generic.c \
+    ${PATH_ROOT}/src/VBox/Runtime/generic/mppresent-generic.cpp=>generic/mppresent-generic.c \
     ${PATH_ROOT}/src/VBox/Runtime/generic/uuid-generic.cpp=>generic/uuid-generic.c \
     ${PATH_ROOT}/src/VBox/Runtime/r0drv/alloc-r0drv.cpp=>r0drv/alloc-r0drv.c \

trunk/src/VBox/Runtime/common/time/timesupA.mac

@@ -95 +95 @@
     mov     u32ApicIdPlus, ebx
  %endif
-    ; pGipCpu = &pGip->aCPU[u8ApicId];
+    ; pGipCpu = &pGip->aCPU[pGip->aiCpuFromApicId[u8ApicId]];
     shr     ebx, 24
+ %ifdef SUP_WITH_LOTS_OF_CPUS
+    movzx   ebx, word [esi + ebx * 2 + SUPGLOBALINFOPAGE.aiCpuFromApicId]
+ %else
+    and     ebx, SUPGLOBALINFOPAGE_CPUS - 1
+ %endif
     mov     eax, SUPGIPCPU_size
     mul     ebx
@@ -516 +521 @@
     mov     u32ApicIdPlus, ebx
  %endif
-    ; pGipCpu = &pGip->aCPU[u8ApicId];
+    ; pGipCpu = &pGip->aCPU[pGip->aiCpuFromApicId[u8ApicId]];
     shr     ebx, 24
+ %ifdef SUP_WITH_LOTS_OF_CPUS
+    movzx   eax, word [pGip + rbx * 2 + SUPGLOBALINFOPAGE.aiCpuFromApicId]
+ %else
     mov     eax, ebx
- %if SUPGLOBALINFOPAGE_CPUS < 256
     and     eax, SUPGLOBALINFOPAGE_CPUS - 1
  %endif

trunk/src/VBox/Runtime/common/time/timesupref.h

@@ -63 +63 @@
 
 #ifdef ASYNC_GIP
-        uint8_t u8ApicId = ASMGetApicId();
-# if SUPGLOBALINFOPAGE_CPUS < 256
-        PSUPGIPCPU pGipCpu = &pGip->aCPUs[u8ApicId & SUPGLOBALINFOPAGE_CPUS];
+        uint8_t    u8ApicId = ASMGetApicId();
+# ifdef SUP_WITH_LOTS_OF_CPUS
+        PSUPGIPCPU pGipCpu = &pGip->aCPUs[pGip->aiCpuFromApicId[u8ApicId]];
 # else
-        PSUPGIPCPU pGipCpu = &pGip->aCPUs[u8ApicId];
+        PSUPGIPCPU pGipCpu = &pGip->aCPUs[u8ApicId & (SUPGLOBALINFOPAGE_CPUS - 1)];
 # endif
 #else

trunk/src/VBox/Runtime/generic/RTMpGetArraySize-generic.cpp

@@ -5 +5 @@
 
 /*
- * Copyright (C) 2010 Oracle Corporation
+ * Copyright (C) 2010-2011 Oracle Corporation
  *
  * This file is part of VirtualBox Open Source Edition (OSE), as
@@ -30 +30 @@
 *******************************************************************************/
 #include <iprt/mp.h>
+#include "internal/iprt.h"
+
+#include <iprt/asm.h>
 #include <iprt/cpuset.h>
-#include "internal/iprt.h"
 
 
 RTDECL(uint32_t) RTMpGetArraySize(void)
 {
-    RTCPUSET    CpuSet;
-    return RTCpuLastIndex(RTMpGetSet(&CpuSet)) + 1;
+    /*
+     * Cache the result here.  This whole point of this function is that it
+     * will always return the same value, so that should be safe.
+     *
+     * Note! Because RTCPUSET may be to small to represent all the CPUs, we
+     *       check with RTMpGetCount() as well.
+     */
+    static uint32_t s_cMaxCpus = 0;
+    uint32_t cCpus = s_cMaxCpus;
+    if (RT_UNLIKELY(cCpus == 0))
+    {
+        RTCPUSET    CpuSet;
+        uint32_t    cCpus1 = RTCpuLastIndex(RTMpGetSet(&CpuSet)) + 1;
+        uint32_t    cCpus2 = RTMpGetCount();
+        uint32_t    cCpus  = RT_MAX(cCpus1, cCpus2);
+        ASMAtomicCmpXchgU32(&s_cMaxCpus, cCpus, 0);
+        return cCpus;
+    }
+    return s_cMaxCpus;
+
 }
 RT_EXPORT_SYMBOL(RTMpGetArraySize);

trunk/src/VBox/VMM/VMMR3/TM.cpp

@@ -122 +122 @@
 #define LOG_GROUP LOG_GROUP_TM
 #include <VBox/vmm/tm.h>
+#include <iprt/asm-amd64-x86.h> /* for SUPGetCpuHzFromGIP from sup.h  */
 #include <VBox/vmm/vmm.h>
 #include <VBox/vmm/mm.h>
@@ -139 +140 @@
 #include <iprt/asm.h>
 #include <iprt/asm-math.h>
-#include <iprt/asm-amd64-x86.h>
 #include <iprt/assert.h>
 #include <iprt/thread.h>
@@ -222 +222 @@
     pVM->tm.s.pvGIPR3 = (void *)g_pSUPGlobalInfoPage;
     AssertMsgReturn(pVM->tm.s.pvGIPR3, ("GIP support is now required!\n"), VERR_INTERNAL_ERROR);
+    AssertMsgReturn((g_pSUPGlobalInfoPage->u32Version >> 16) == (SUPGLOBALINFOPAGE_VERSION >> 16),
+                    ("Unsupported GIP version!\n"), VERR_INTERNAL_ERROR);
+
     RTHCPHYS HCPhysGIP;
     rc = SUPR3GipGetPhys(&HCPhysGIP);
@@ -227 +230 @@
 
     RTGCPTR GCPtr;
+#ifdef SUP_WITH_LOTS_OF_CPUS
+    rc = MMR3HyperMapHCPhys(pVM, pVM->tm.s.pvGIPR3, NIL_RTR0PTR, HCPhysGIP, (size_t)g_pSUPGlobalInfoPage->cPages * PAGE_SIZE,
+                            "GIP", &GCPtr);
+#else
     rc = MMR3HyperMapHCPhys(pVM, pVM->tm.s.pvGIPR3, NIL_RTR0PTR, HCPhysGIP, PAGE_SIZE, "GIP", &GCPtr);
+#endif
     if (RT_FAILURE(rc))
     {
@@ -795 +803 @@
      * Use GIP when available present.
      */
-    uint64_t    u64Hz;
-    PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
-    if (    pGip
-        &&  pGip->u32Magic == SUPGLOBALINFOPAGE_MAGIC)
-    {
-        unsigned iCpu = pGip->u32Mode != SUPGIPMODE_ASYNC_TSC ? 0 : ASMGetApicId();
-        if (iCpu >= RT_ELEMENTS(pGip->aCPUs))
-            AssertReleaseMsgFailed(("iCpu=%d - the ApicId is too high. send VBox.log and hardware specs!\n", iCpu));
+    uint64_t u64Hz = SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage);
+    if (u64Hz != UINT64_MAX)
+    {
+        if (tmR3HasFixedTSC(pVM))
+            /* Sleep a bit to get a more reliable CpuHz value. */
+            RTThreadSleep(32);
         else
         {
-            if (tmR3HasFixedTSC(pVM))
-                /* Sleep a bit to get a more reliable CpuHz value. */
-                RTThreadSleep(32);
-            else
-            {
-                /* Spin for 40ms to try push up the CPU frequency and get a more reliable CpuHz value. */
-                const uint64_t u64 = RTTimeMilliTS();
-                while ((RTTimeMilliTS() - u64) < 40 /*ms*/)
-                    /* nothing */;
-            }
-
-            pGip = g_pSUPGlobalInfoPage;
-            if (    pGip
-                &&  pGip->u32Magic == SUPGLOBALINFOPAGE_MAGIC
-                &&  (u64Hz = pGip->aCPUs[iCpu].u64CpuHz)
-                &&  u64Hz != ~(uint64_t)0)
-                return u64Hz;
+            /* Spin for 40ms to try push up the CPU frequency and get a more reliable CpuHz value. */
+            const uint64_t u64 = RTTimeMilliTS();
+            while ((RTTimeMilliTS() - u64) < 40 /*ms*/)
+                /* nothing */;
         }
+
+        u64Hz = SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage);
+        if (u64Hz != UINT64_MAX)
+            return u64Hz;
     }