VirtualBox

Changeset 36268 in vbox for trunk/src/VBox/Devices/Bus


Ignore:
Timestamp:
Mar 11, 2011 4:37:25 PM (14 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
70538
Message:

PCI: fixed issues with memory layout mismatch between RC and other contexts, tests added

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r36253 r36268  
    2222/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
    2323#define PCI_INCLUDE_PRIVATE
     24#define PCIBus ICH9PCIBus
    2425#include <VBox/pci.h>
    2526#include <VBox/msi.h>
    … …  
    4344 * PCI Bus instance.
    4445 */
    45 typedef struct PCIBus
     46typedef struct ICH9PCIBus
    4647{
    4748    /** Bus number. */
    … …  
    7374    PCIDEVICE           aPciDev;
    7475
    75 } PCIBUS, *PPCIBUS;
     76} ICH9PCIBUS, *PICH9PCIBUS;
    7677
    7778
    … …  
    9798#endif
    9899
    99     /** PCI bus which is attached to the host-to-PCI bridge. */
    100     PCIBUS              aPciBus;
     100     /** Config register. */
     101    uint32_t            uConfigReg;
    101102
    102103    /** I/O APIC irq levels */
    … …  
    116117    uint64_t            u64PciConfigMMioLength;
    117118
    118 
    119     /** Config register. */
    120     uint32_t            uConfigReg;
    121 } PCIGLOBALS, *PPCIGLOBALS;
     119    /** PCI bus which is attached to the host-to-PCI bridge. */
     120    ICH9PCIBUS          aPciBus;
     121} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
    122122
    123123
    … …  
    129129} PciAddress;
    130130
     131#ifndef VBOX_DEVICE_STRUCT_TESTCASE
    131132
    132133/*******************************************************************************
    … …  
    143144/** Converts a bus instance pointer to a device instance pointer. */
    144145#define PCIBUS_2_DEVINS(pPciBus)        ((pPciBus)->CTX_SUFF(pDevIns))
    145 /** Converts a device instance pointer to a PCIGLOBALS pointer. */
    146 #define DEVINS_2_PCIGLOBALS(pDevIns)    ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
     146/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
     147#define DEVINS_2_PCIGLOBALS(pDevIns)    ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
    147148/** Converts a device instance pointer to a PCIBUS pointer. */
    148 #define DEVINS_2_PCIBUS(pDevIns)        ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
     149#define DEVINS_2_PCIBUS(pDevIns)        ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
    149150/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
    150 #define PCIROOTBUS_2_PCIGLOBALS(pPciBus)    ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
    151 
     151#define PCIROOTBUS_2_PCIGLOBALS(pPciBus)    ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
    152152
    153153/** @def PCI_LOCK
    … …  
    164164    DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
    165165
    166 #ifndef VBOX_DEVICE_STRUCT_TESTCASE
    167 
    168166RT_C_DECLS_BEGIN
    169167
    … …  
    180178
    181179/* Prototypes */
    182 static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
     180static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
    183181#ifdef IN_RING3
    184182static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
    185 static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
     183static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
    186184static void ich9pciUpdateMappings(PCIDevice *pDev);
    187185static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
    188 DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
    189 static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
     186DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
     187static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
    190188#endif
    191189
    192190// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
    193191// mapping, we take n=6 approach
    194 DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
     192DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
    195193{
    196194    pPciAddr->iBus          = (GCPhysAddr >> 20) & ((1<<6)       - 1);
    … …  
    199197}
    200198
    201 DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
     199DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
    202200{
    203201    pPciAddr->iBus         = (pGlobals->uConfigReg >> 16) & 0xff;
    … …  
    208206PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
    209207{
    210     ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
     208    ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
    211209}
    212210
    … …  
    220218     * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
    221219     */
    222     PPCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PPCIBUS);
    223     PPCIDEVICE pPciDevBus    = pPciDev;
    224     int        iIrqPinBridge = iIrq;
    225     uint8_t    uDevFnBridge  = 0;
     220    PICH9PCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     221    PPCIDEVICE     pPciDevBus    = pPciDev;
     222    int            iIrqPinBridge = iIrq;
     223    uint8_t        uDevFnBridge  = 0;
    226224
    227225    /* Walk the chain until we reach the host bus. */
    … …  
    257255    if (cb == 4)
    258256    {
    259         PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     257        PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    260258
    261259        PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
    … …  
    283281    if (cb == 4)
    284282    {
    285         PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     283        PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    286284        PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
    287285        *pu32 = pThis->uConfigReg;
    288286        PCI_UNLOCK(pDevIns);
    289         LogFlow(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
     287        LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
    290288        return VINF_SUCCESS;
    291289    }
    … …  
    296294}
    297295
    298 static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr,
     296static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
    299297                                uint32_t val, int cb, int rcReschedule)
    300298{
    … …  
    350348}
    351349
    352 static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
     350static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
    353351{
    354352    PciAddress aPciAddr;
    … …  
    387385PDMBOTHCBDECL(int)  ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    388386{
    389     LogFlow(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
     387    LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
    390388    NOREF(pvUser);
    391389    int rc = VINF_SUCCESS;
    … …  
    393391    {
    394392        PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
    395         rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
     393        rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, u32, cb);
    396394        PCI_UNLOCK(pDevIns);
    397395    }
    … …  
    401399}
    402400
    403 static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
     401static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
    404402                               uint32_t *pu32, int rcReschedule)
    405403{
    … …  
    458456}
    459457
    460 static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
     458static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
    461459{
    462460    PciAddress aPciAddr;
    … …  
    495493    {
    496494        PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
    497         int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
     495        int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, cb, pu32);
    498496        PCI_UNLOCK(pDevIns);
    499         LogFlow(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
     497        LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
    500498        return rc;
    501499    }
    … …  
    523521
    524522/* Add one more level up request on APIC input line */
    525 DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
     523DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
    526524{
    527525    ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
    … …  
    529527
    530528/* Remove one level up request on APIC input line */
    531 DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
     529DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
    532530{
    533531    ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
    534532}
    535533
    536 static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
     534static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
    537535{
    538536    /* This is only allowed to be called with a pointer to the root bus. */
    … …  
    542540    {
    543541        int apic_irq, apic_level;
    544         PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
     542        PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
    545543        int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
    546544
    … …  
    576574}
    577575
    578 static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
     576static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
    579577{
    580578
    … …  
    595593    }
    596594
    597     PPCIBUS     pBus =     &pGlobals->aPciBus;
     595    PICH9PCIBUS     pBus      =     &pGlobals->aPciBus;
    598596    const bool  fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
    599597
    … …  
    620618PDMBOTHCBDECL(int)  ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
    621619{
    622     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     620    PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    623621    PciAddress aDest;
    624622    uint32_t u32 = 0;
    … …  
    653651PDMBOTHCBDECL(int)  ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
    654652{
    655     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     653    PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    656654    PciAddress  aDest;
    657655    uint32_t    rv;
    … …  
    690688#ifdef IN_RING3
    691689
    692 DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
     690DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
    693691{
    694692    /* Search for a fitting bridge. */
    … …  
    745743    PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
    746744    int rc = VINF_SUCCESS;
    747     PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
     745    PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
    748746
    749747    Assert (pRegion->size != 0);
    … …  
    779777static void ich9pciUpdateMappings(PCIDevice* pDev)
    780778{
    781     PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
     779    PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
    782780    uint64_t uLast, uNew;
    783781
    … …  
    867865static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
    868866{
    869     PPCIBUS     pBus = DEVINS_2_PCIBUS(pDevIns);
     867    PICH9PCIBUS     pBus = DEVINS_2_PCIBUS(pDevIns);
    870868
    871869    /*
    … …  
    907905{
    908906
    909     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     907    PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    910908
    911909    /*
    … …  
    996994}
    997995
    998 static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
     996static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
    999997{
    1000998    /*
    … …  
    10511049static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    10521050{
    1053     PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1051    PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    10541052
    10551053    /*
    … …  
    10721070static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    10731071{
    1074     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
     1072    PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    10751073    return ich9pciR3CommonSaveExec(pThis, pSSM);
    10761074}
    … …  
    10791077static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
    10801078{
    1081     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     1079    PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    10821080
    10831081    LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
    … …  
    11071105static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
    11081106{
    1109     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     1107    PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    11101108    uint32_t u32Value;
    11111109
    … …  
    13171315 * @param   uPass               The pass.
    13181316 */
    1319 static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
     1317static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    13201318{
    13211319    uint32_t    u32;
    … …  
    14791477static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    14801478{
    1481     PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
    1482     PPCIBUS     pBus  = &pThis->aPciBus;
    1483     uint32_t    u32;
    1484     int         rc;
     1479    PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     1480    PICH9PCIBUS     pBus  = &pThis->aPciBus;
     1481    uint32_t        u32;
     1482    int             rc;
    14851483
    14861484    /* We ignore this version as there's no saved state with it anyway */
    … …  
    15131511static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    15141512{
    1515     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
     1513    PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    15161514    if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
    15171515        return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
    … …  
    15191517}
    15201518
    1521 static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
     1519static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
    15221520{
    15231521    /* Will only work in LSB case */
    … …  
    15351533}
    15361534
    1537 static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
     1535static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
    15381536{
    15391537    PciAddress aPciAddr;
    … …  
    15481546}
    15491547
    1550 static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
     1548static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
    15511549{
    15521550    uint32_t uReg = ich9pciGetRegionReg(iRegion);
    … …  
    15791577
    15801578
    1581 static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
     1579static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
    15821580{
    15831581    Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
    … …  
    16451643}
    16461644
    1647 static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
     1645static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
    16481646{
    16491647    uint16_t uDevClass, uVendor, uDevice;
    … …  
    17741772        {
    17751773            /* Find bus this device attached to. */
    1776             PPCIBUS pBus = &pGlobals->aPciBus;
     1774            PICH9PCIBUS pBus = &pGlobals->aPciBus;
    17771775            while (1)
    17781776            {
    … …  
    17881786                    break;
    17891787                }
    1790                 pBus = PDMINS_2_DATA(pBridge->pDevIns, PPCIBUS);
     1788                pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
    17911789            }
    17921790
    … …  
    18101808
    18111809/* Initializes bridges registers used for routing. */
    1812 static void ich9pciInitBridgeTopology(PPCIGLOBALS pGlobals, PPCIBUS pBus)
     1810static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus)
    18131811{
    18141812    PPCIDEVICE pBridgeDev = &pBus->aPciDev;
    … …  
    18271825        AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
    18281826                  ("Device is not a PCI bridge but on the list of PCI bridges\n"));
    1829         PPCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PPCIBUS);
     1827        PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
    18301828        ich9pciInitBridgeTopology(pGlobals, pChildBus);
    18311829    }
    … …  
    18441842    unsigned    i;
    18451843    uint8_t     elcr[2] = {0, 0};
    1846     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1844    PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    18471845    PVM         pVM = PDMDevHlpGetVM(pDevIns);
    18481846    Assert(pVM);
    … …  
    18581856     * Assign bridge topology, for further routing to work.
    18591857     */
    1860     PPCIBUS pBus = &pGlobals->aPciBus;
     1858    PICH9PCIBUS pBus = &pGlobals->aPciBus;
    18611859    ich9pciInitBridgeTopology(pGlobals, pBus);
    18621860
    … …  
    21202118};
    21212119
    2122 static bool assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn, PciAddress* aPosition)
     2120static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn, PciAddress* aPosition)
    21232121{
    21242122    aPosition->iBus = 0;
    … …  
    21652163}
    21662164
    2167 static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
     2165static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
    21682166{
    21692167    PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
    … …  
    21802178}
    21812179
    2182 static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
     2180static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
    21832181{
    21842182    PciAddress aPosition = {0, 0, 0};
    … …  
    22722270}
    22732271
    2274 static void ich9pciBusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
     2272static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
    22752273{
    22762274    for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
    … …  
    23622360        for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
    23632361        {
    2364             PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
     2362            PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
    23652363            ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
    23662364        }
    … …  
    23772375static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
    23782376{
    2379     PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
     2377    PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
    23802378
    23812379    if (pszArgs == NULL || !strcmp(pszArgs, "basic"))
    … …  
    24262424        return PDMDEV_SET_ERROR(pDevIns, rc,
    24272425                                N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
    2428 
    24292426    /* check if R0 code is enabled. */
    24302427    bool fR0Enabled;
    … …  
    24392436     * Init data.
    24402437     */
    2441     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
    2442     PPCIBUS     pBus     = &pGlobals->aPciBus;
     2438    PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     2439    PICH9PCIBUS     pBus     = &pGlobals->aPciBus;
    24432440    /* Zero out everything */
    24442441    memset(pGlobals, 0, sizeof(*pGlobals));
    … …  
    26232620static void ich9pciResetDevice(PPCIDEVICE pDev)
    26242621{
    2625     PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
     2622    PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
    26262623    int rc;
    26272624
    … …  
    26652662static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
    26662663{
    2667     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
    2668     PPCIBUS     pBus     = &pGlobals->aPciBus;
     2664    PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     2665    PICH9PCIBUS     pBus     = &pGlobals->aPciBus;
    26692666
    26702667    /* PCI-specific reset for each device. */
    … …  
    26992696static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    27002697{
    2701     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
    2702     PPCIBUS     pBus     = &pGlobals->aPciBus;
     2698    PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     2699    PICH9PCIBUS     pBus     = &pGlobals->aPciBus;
    27032700    pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    27042701
    … …  
    27452742     * Init data and register the PCI bus.
    27462743     */
    2747     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2744    PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    27482745    pBus->pDevInsR3 = pDevIns;
    27492746    pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    … …  
    28412838static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
    28422839{
    2843     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2840    PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    28442841
    28452842    /* Reset config space to default values. */
    … …  
    28622859static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    28632860{
    2864     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2861    PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
    28652862    pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    28662863
    … …  
    28922889    1,
    28932890    /* cbInstance */
    2894     sizeof(PCIGLOBALS),
     2891    sizeof(ICH9PCIGLOBALS),
    28952892    /* pfnConstruct */
    28962893    ich9pciConstruct,
    … …  
    29482945    ~0,
    29492946    /* cbInstance */
    2950     sizeof(PCIBUS),
     2947    sizeof(ICH9PCIBUS),
    29512948    /* pfnConstruct */
    29522949    ich9pcibridgeConstruct,
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