VirtualBox

Changeset 36288 in vbox


Ignore:
Timestamp:
Mar 15, 2011 3:16:17 PM (14 years ago)
Author:
vboxsync
Message:

Ich9: Remove the i82801 PCI-to-PCI bridge. It is completely unused and is not the Host-to-PCI bridge either

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r36268 r36288  
    18111811{
    18121812    PPCIDEVICE pBridgeDev = &pBus->aPciDev;
    1813     PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus);
    1814 
    1815     /* For simplicity, let's start numbering PCI bridges from 0,
    1816      * not 1, so don't increment count on Host->PCI bridge.
    1817      */
    1818     if (strcmp(pBridgeDev->name, "i82801") != 0)
    1819         pGlobals->uBus++;
    1820 
    1821     PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
     1813
     1814    /* Set only if we are not on the root bus, it has no primary bus attached. */
     1815    if (pGlobals->uBus != 0)
     1816    {
     1817        PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus);
     1818        PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
     1819    }
     1820
     1821    pGlobals->uBus++;
    18221822    for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
    18231823    {
     
    21052105}
    21062106
    2107 /* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
    2108 static const struct {
    2109     const char* pszName;
    2110     int32_t     iSlot;
    2111     int32_t     iFunction;
    2112 } PciSlotAssignments[] = {
    2113     /* The only override that have to be here, as host controller is added in the way invisible to bus slot assignment management,
    2114        maybe to be changed in the future. */
    2115     {
    2116         "i82801",   30, 0 /* Host Controller */
    2117     },
    2118 };
    2119 
    21202107static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn, PciAddress* aPosition)
    21212108{
     
    21232110    aPosition->iDeviceFunc = iDevFn;
    21242111    aPosition->iRegister = 0; /* N/A */
    2125 
    2126     /* Hardcoded slots/functions, per chipset spec */
    2127     for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
    2128     {
    2129         if (!strcmp(pszName, PciSlotAssignments[i].pszName))
    2130         {
    2131             pciDevSetRequestedDevfunc(pPciDev);
    2132             aPosition->iDeviceFunc =
    2133                     (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
    2134             return true;
    2135         }
    2136     }
    21372112
    21382113    /* Explicit slot request */
     
    24922467     * Fill in PCI configs and add them to the bus.
    24932468     */
    2494 
    2495     /*
    2496      * We emulate 82801IB ICH9 IO chip used in Q35,
    2497      * see http://ark.intel.com/Product.aspx?id=31892
    2498      *
    2499      * Stepping   S-Spec   Top Marking
    2500      *
    2501      *   A2        SLA9M    NH82801IB
    2502      */
     2469    /** @todo: Disabled for now because this causes error messages with Linux guests.
     2470     *         The guest loads the x38_edac device which tries to map a memory region
     2471     *         using an address given at place 0x48 - 0x4f in the PCi config space.
     2472     *         This fails. because we don't register such a region.
     2473     */
     2474#if 0
    25032475    /* Host bridge device */
    2504     /* @todo: move to separate driver? */
    25052476    PCIDevSetVendorId(  &pBus->aPciDev, 0x8086); /* Intel */
    2506     PCIDevSetDeviceId(  &pBus->aPciDev, 0x244e); /* Desktop */
    2507     PCIDevSetRevisionId(&pBus->aPciDev,   0x92); /* rev. A2 */
     2477    PCIDevSetDeviceId(  &pBus->aPciDev, 0x29e0); /* Desktop */
     2478    PCIDevSetRevisionId(&pBus->aPciDev,   0x01); /* rev. 01 */
    25082479    PCIDevSetClassBase( &pBus->aPciDev,   0x06); /* bridge */
    25092480    PCIDevSetClassSub(  &pBus->aPciDev,   0x00); /* Host/PCI bridge */
    2510     PCIDevSetClassProg( &pBus->aPciDev,   0x01); /* Supports subtractive decoding. */
    2511     PCIDevSetHeaderType(&pBus->aPciDev,   0x01); /* bridge */
     2481    PCIDevSetClassProg( &pBus->aPciDev,   0x00); /* Host/PCI bridge */
     2482    PCIDevSetHeaderType(&pBus->aPciDev,   0x00); /* bridge */
    25122483    PCIDevSetWord(&pBus->aPciDev,  VBOX_PCI_SEC_STATUS, 0x0280);  /* secondary status */
    2513     PCIDevSetDWord(&pBus->aPciDev, 0x4c, 0x00001200); /* Bridge policy configuration */
    2514     PCIDevSetStatus    (&pBus->aPciDev, VBOX_PCI_STATUS_CAP_LIST);
    2515     PCIDevSetCapabilityList(&pBus->aPciDev, 0x50);
    2516     /* capability */
    2517     PCIDevSetWord(&pBus->aPciDev,  0x50, VBOX_PCI_CAP_ID_SSVID);
    2518     PCIDevSetDWord(&pBus->aPciDev, 0x54, 0x00000000); /* Subsystem vendor ids */
    25192484
    25202485    pBus->aPciDev.pDevIns               = pDevIns;
    25212486    /* We register Host<->PCI controller on the bus */
    2522     ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
     2487    ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
     2488#endif
    25232489
    25242490    /*
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