Changeset 36398 in vbox for trunk/include/VBox/x86.h

Timestamp:

Mar 24, 2011 12:40:25 PM (14 years ago)

Author:

vboxsync

Message:

x86.h: doxygen comments.

File:

• trunk/include/VBox/x86.h (modified) (2 diffs)

trunk/include/VBox/x86.h

@@ -876 +876 @@
 #define MSR_IA32_DEBUGCTL                   0x1D9
 
-/* Page Attribute Table. */
+/** Page Attribute Table. */
 #define MSR_IA32_CR_PAT                     0x277
 
@@ -889 +889 @@
 /** Enable misc. processor features (R/W). */
 #define MSR_IA32_MISC_ENABLE                   0x1A0
-/* Enable fast-strings feature (for REP MOVS and REP STORS). */
+/** Enable fast-strings feature (for REP MOVS and REP STORS). */
 #define MSR_IA32_MISC_ENABLE_FAST_STRINGS      RT_BIT(0)
-/* Automatic Thermal Control Circuit Enable (R/W). */
+/** Automatic Thermal Control Circuit Enable (R/W). */
 #define MSR_IA32_MISC_ENABLE_TCC               RT_BIT(3)
-/* Performance Monitoring Available (R). */
+/** Performance Monitoring Available (R). */
 #define MSR_IA32_MISC_ENABLE_PERF_MON          RT_BIT(7)
-/* Branch Trace Storage Unavailable (R/O). */
+/** Branch Trace Storage Unavailable (R/O). */
 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL       RT_BIT(11)
-/* Precise Event Based Sampling (PEBS) Unavailable (R/O). */
+/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL      RT_BIT(12)
-/* Enhanced Intel SpeedStep Technology Enable (R/W). */
+/** Enhanced Intel SpeedStep Technology Enable (R/W). */
 #define MSR_IA32_MISC_ENABLE_SST_ENABLE        RT_BIT(16)
-/* If MONITOR/MWAIT is supported (R/W). */
+/** If MONITOR/MWAIT is supported (R/W). */
 #define MSR_IA32_MISC_ENABLE_MONITOR           RT_BIT(18)
-/* Limit CPUID Maxval to 3 leafs (R/W). */
+/** Limit CPUID Maxval to 3 leafs (R/W). */
 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID       RT_BIT(22)
-/* When set to 1, xTPR messages are disabled (R/W). */
+/** When set to 1, xTPR messages are disabled (R/W). */
 #define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE  RT_BIT(23)
-/* When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
+/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
 #define MSR_IA32_MISC_ENABLE_XD_DISABLE        RT_BIT(34)