Changeset 36795 in vbox
- Timestamp:
- Apr 21, 2011 3:41:39 PM (14 years ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r36794 r36795 190 190 /** Temporary hack to disable the double execution. Will be removed in favor 191 191 * of a dedicated execution mode in EM. */ 192 //#define IEM_VERIFICATION_MODE_NO_REM192 #define IEM_VERIFICATION_MODE_NO_REM 193 193 194 194 /** Used to shut up GCC warnings about variables that 'may be used uninitialized' … … 3604 3604 else 3605 3605 { 3606 GCPtrBottom--; 3606 3607 uint16_t *pa16Mem = NULL; 3607 3608 rcStrict = iemMemMap(pIemCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W); … … 3675 3676 else 3676 3677 { 3678 GCPtrBottom--; 3677 3679 uint32_t *pa32Mem; 3678 3680 rcStrict = iemMemMap(pIemCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W); … … 4168 4170 4169 4171 /* Check stack first - may #SS(0). */ 4170 rcStrict = iemMemStackPushBeginSpecial(pIemCpu, 4 + (enmOpSize == IEMMODE_32BIT) * 2,4172 rcStrict = iemMemStackPushBeginSpecial(pIemCpu, enmOpSize == IEMMODE_32BIT ? 6 : 4, 4171 4173 &pvRet, &uNewRsp); 4172 4174 if (rcStrict != VINF_SUCCESS) … … 4180 4182 if (enmOpSize == IEMMODE_16BIT) 4181 4183 { 4182 ((uint16_t *)pvRet)[0] = pCtx->ip ;4184 ((uint16_t *)pvRet)[0] = pCtx->ip + cbInstr; 4183 4185 ((uint16_t *)pvRet)[1] = pCtx->cs; 4184 4186 } 4185 4187 else 4186 4188 { 4187 ((uint32_t *)pvRet)[0] = pCtx->eip ;4189 ((uint32_t *)pvRet)[0] = pCtx->eip + cbInstr; 4188 4190 ((uint16_t *)pvRet)[3] = pCtx->cs; 4189 4191 } … … 4373 4375 pu16Frame[2] = (uint16_t)pCtx->eflags.u; 4374 4376 pu16Frame[1] = (uint16_t)pCtx->cs; 4375 pu16Frame[0] = (uint16_t)pCtx->ip;4377 pu16Frame[0] = pCtx->ip + cbInstr; 4376 4378 rcStrict = iemMemStackPushCommitSpecial(pIemCpu, pu16Frame, uNewRsp); 4377 4379 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS)) … … 6188 6190 } 6189 6191 6192 6193 # ifndef IEM_VERIFICATION_MODE_NO_REM 6190 6194 /** 6191 6195 * Allocate an event record. … … 6210 6214 return pEvtRec; 6211 6215 } 6216 # endif 6212 6217 6213 6218 … … 6315 6320 } 6316 6321 6322 # ifndef IEM_VERIFICATION_MODE_NO_REM 6317 6323 6318 6324 /** … … 6441 6447 6442 6448 /** 6449 * Verifies a write record. 6450 * 6451 * @param pIemCpu The IEM per CPU data. 6452 * @param pEvtRec The write record. 6453 */ 6454 static void iemVerifyWriteRecord(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec) 6455 { 6456 uint8_t abBuf[sizeof(pEvtRec->u.RamWrite.ab)]; RT_ZERO(abBuf); 6457 int rc = PGMPhysSimpleReadGCPhys(IEMCPU_TO_VM(pIemCpu), abBuf, pEvtRec->u.RamWrite.GCPhys, pEvtRec->u.RamWrite.cb); 6458 if ( RT_FAILURE(rc) 6459 || memcmp(abBuf, pEvtRec->u.RamWrite.ab, pEvtRec->u.RamWrite.cb) ) 6460 { 6461 /* fend off ins */ 6462 if ( !pIemCpu->cIOReads 6463 || pEvtRec->u.RamWrite.ab[0] != 0xcc 6464 || ( pEvtRec->u.RamWrite.cb != 1 6465 && pEvtRec->u.RamWrite.cb != 2 6466 && pEvtRec->u.RamWrite.cb != 4) ) 6467 { 6468 RTAssertMsg1(NULL, __LINE__, __FILE__, __PRETTY_FUNCTION__); 6469 RTAssertMsg2Weak("Memory at %RGv differs\n", pEvtRec->u.RamWrite.GCPhys); 6470 RTAssertMsg2Add("REM: %.*Rhxs\n" 6471 "IEM: %.*Rhxs\n", 6472 pEvtRec->u.RamWrite.cb, abBuf 6473 pEvtRec->u.RamWrite.cb, pEvtRec->u.RamWrite.ab); 6474 iemVerifyAssertAddRecordDump(pEvtRec); 6475 RTAssertPanic(); 6476 } 6477 } 6478 6479 } 6480 6481 # endif /* !IEM_VERIFICATION_MODE_NO_REM */ 6482 6483 /** 6443 6484 * Performs the post-execution verfication checks. 6444 6485 */ … … 6459 6500 int rc = REMR3EmulateInstruction(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu)); 6460 6501 AssertRC(rc); 6461 #if 06462 if (pIemCpu->fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))6463 {6464 while ( pOrgCtx->rip == pDebugCtx->rip - pIemCpu->offOpcode6465 && pOrgCtx->rcx != pDebugCtx->rcx6466 && pOrgCtx->rsi != pDebugCtx->rsi6467 && pOrgCtx->rdi != pDebugCtx->rdi)6468 {6469 rc = REMR3EmulateInstruction(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu));6470 AssertRC(rc);6471 }6472 }6473 #endif6474 6502 6475 6503 /* … … 6642 6670 while (pIemRec && pOtherRec) 6643 6671 { 6644 /* Since we might miss RAM writes and reads, ignore extra ones6645 made by IEM. */6672 /* Since we might miss RAM writes and reads, ignore reads and check 6673 that any written memory is the same extra ones. */ 6646 6674 while ( IEMVERIFYEVENT_IS_RAM(pIemRec->enmEvent) 6647 6675 && !IEMVERIFYEVENT_IS_RAM(pOtherRec->enmEvent) 6648 6676 && pIemRec->pNext) 6677 { 6678 if (pIemRec->enmEvent == IEMVERIFYEVENT_RAM_WRITE) 6679 iemVerifyWriteRecord(pIemCpu, pIemRec); 6649 6680 pIemRec = pIemRec->pNext; 6681 } 6650 6682 6651 6683 /* Do the compare. */ … … 6693 6725 /* Ignore extra writes and reads. */ 6694 6726 while (pIemRec && IEMVERIFYEVENT_IS_RAM(pIemRec->enmEvent)) 6727 { 6728 if (pIemRec->enmEvent == IEMVERIFYEVENT_RAM_WRITE) 6729 iemVerifyWriteRecord(pIemCpu, pIemRec); 6695 6730 pIemRec = pIemRec->pNext; 6731 } 6696 6732 if (pIemRec != NULL) 6697 6733 iemVerifyAssertRecord(pIemRec, "Extra IEM record!"); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h
r36794 r36795 8137 8137 IEM_MC_FETCH_MEM_U32(offSeg, pIemCpu->iEffSeg, GCPtrEffSrc); 8138 8138 IEM_MC_FETCH_MEM_U16(u16Sel, pIemCpu->iEffSeg, GCPtrEffSrc + 4); 8139 IEM_MC_CALL_CIMPL_3(iemCImpl_callf, u16Sel, offSeg, IEMMODE_ 16BIT);8139 IEM_MC_CALL_CIMPL_3(iemCImpl_callf, u16Sel, offSeg, IEMMODE_32BIT); 8140 8140 IEM_MC_END(); 8141 8141 } … … 8150 8150 IEM_MC_FETCH_MEM_S32_SX_U64(offSeg, pIemCpu->iEffSeg, GCPtrEffSrc); 8151 8151 IEM_MC_FETCH_MEM_U16(u16Sel, pIemCpu->iEffSeg, GCPtrEffSrc + 4); 8152 IEM_MC_CALL_CIMPL_3(iemCImpl_callf, u16Sel, offSeg, IEMMODE_ 16BIT);8152 IEM_MC_CALL_CIMPL_3(iemCImpl_callf, u16Sel, offSeg, IEMMODE_32BIT); 8153 8153 IEM_MC_END(); 8154 8154 } … … 8164 8164 IEM_MC_FETCH_MEM_U64(offSeg, pIemCpu->iEffSeg, GCPtrEffSrc); 8165 8165 IEM_MC_FETCH_MEM_U16(u16Sel, pIemCpu->iEffSeg, GCPtrEffSrc + 8); 8166 IEM_MC_CALL_CIMPL_3(iemCImpl_callf, u16Sel, offSeg, IEMMODE_ 16BIT);8166 IEM_MC_CALL_CIMPL_3(iemCImpl_callf, u16Sel, offSeg, IEMMODE_64BIT); 8167 8167 IEM_MC_END(); 8168 8168 return VINF_SUCCESS;
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