Changeset 36837 in vbox

Timestamp:

Apr 25, 2011 8:41:44 AM (14 years ago)

Author:

vboxsync

Message:

HPET: cleanup, ICH9-specific HPET behavior

Location:

trunk/src/VBox

Files:

• Devices/PC/DevHPET.cpp (modified) (27 diffs)
• Main/src-client/ConsoleImpl2.cpp (modified) (1 diff)

trunk/src/VBox/Devices/PC/DevHPET.cpp

@@ -50 +50 @@
  */
 #define HPET_NUM_TIMERS             3
+#define HPET_NUM_TIMERS_ICH9        4
 
 /*
@@ -55 +56 @@
  */
 #define HPET_CLK_PERIOD             10000000UL
+
+/*
+ * 69841279 femtoseconds == 69.84 ns
+ */
+#define HPET_CLK_PERIOD_ICH9        69841279UL
 
 /*
@@ -130 +136 @@
     RCPTRTYPE(struct HpetState *)    pHpetRC;
 
-    /* timer number*/
+    /* Timer number. */
     uint8_t                          u8TimerNumber;
-     /* Wrap */
+     /* Wrap. */
     uint8_t                          u8Wrap;
-    /* Alignment */
+    /* Alignment. */
     uint32_t                         alignment0;
-    /* Memory-mapped, software visible timer registers */
-    /* Configuration/capabilities */
+    /* Memory-mapped, software visible timer registers. */
+    /* Configuration/capabilities. */
     uint64_t                         u64Config;
-    /* comparator */
+    /* comparator. */
     uint64_t                         u64Cmp;
-    /* FSB route, not supported now */
+    /* FSB route, not supported now. */
     uint64_t                         u64Fsb;
 
-    /* Hidden register state */
-    /* Last value written to comparator */
+    /* Hidden register state. */
+    /* Last value written to comparator. */
     uint64_t                         u64Period;
 } HpetTimer;
@@ -166 +172 @@
     PCPDMHPETHLPRC       pHpetHlpRC;
 
-    /* Timer structures */
+    /* Timer structures. */
     HpetTimer            aTimers[HPET_NUM_TIMERS];
 
-    /* Offset realtive to the system clock */
+    /* Offset realtive to the system clock. */
     uint64_t             u64HpetOffset;
 
     /* Memory-mapped, software visible registers */
-    /* capabilities */
+    /* capabilities. */
     uint64_t             u64Capabilities;
-    /* configuration */
+    /* Configuration. */
     uint64_t             u64HpetConfig;
-    /* interrupt status register */
+    /* Interrupt status register. */
     uint64_t             u64Isr;
-    /* main counter */
+    /* Main counter. */
     uint64_t             u64HpetCounter;
 
-    /* Global device lock */
+    /* Global device lock. */
     PDMCRITSECT          csLock;
+
+    /* If we emulate ICH9 HPET (different frequency and counter rollover behavior
+       in 32-bit mode). */
+    uint8_t              fIch9;
+    uint8_t              padding0[7];
 } HpetState;
 
@@ -232 +243 @@
 }
 
-static uint64_t hpetTicksToNs(uint64_t value)
-{
-    return (ASMMultU64ByU32DivByU32(value, HPET_CLK_PERIOD, FS_PER_NS));
-}
-
-static uint64_t nsToHpetTicks(uint64_t u64Value)
-{
-    return (ASMMultU64ByU32DivByU32(u64Value, FS_PER_NS, HPET_CLK_PERIOD));
+static uint64_t hpetTicksToNs(HpetState* pThis, uint64_t value)
+{
+    return (ASMMultU64ByU32DivByU32(value,  (uint32_t)(pThis->u64Capabilities >> 32), FS_PER_NS));
+}
+
+static uint64_t nsToHpetTicks(HpetState* pThis, uint64_t u64Value)
+{
+    return (ASMMultU64ByU32DivByU32(u64Value, FS_PER_NS, (uint32_t)(pThis->u64Capabilities >> 32)));
 }
 
@@ -248 +259 @@
      * with the same speed.
      */
-    return nsToHpetTicks(TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer)) +
-                         pThis->u64HpetOffset);
+    return  nsToHpetTicks(pThis, TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer)) +
+                          pThis->u64HpetOffset);
 }
 
@@ -329 +340 @@
     u64Diff = hpetComputeDiff(pTimer, u64Ticks);
 
-    /* Spec says in one-shot 32-bit mode, generate an interrupt when
+    /* HPET spec says in one-shot 32-bit mode, generate an interrupt when
      * counter wraps in addition to an interrupt with comparator match.
+     *
+     * ICH9 spec doesn't mention that, so we disable wraparound behavior for ICH9,
+     * see public trac defect #8707.
      */
-    if ((pTimer->u64Config & HPET_TN_32BIT) && !(pTimer->u64Config & HPET_TN_PERIODIC))
-    {
-        u32TillWrap = 0xffffffff - (uint32_t)u64Ticks;
-        if (u32TillWrap < (uint32_t)u64Diff)
-        {
-            u64Diff = u32TillWrap;
-            pTimer->u8Wrap = 1;
+    if (!pTimer->CTX_SUFF(pHpet)->fIch9)
+    {
+        if ((pTimer->u64Config & HPET_TN_32BIT) && !(pTimer->u64Config & HPET_TN_PERIODIC))
+        {
+            u32TillWrap = 0xffffffff - (uint32_t)u64Ticks;
+            if (u32TillWrap < (uint32_t)u64Diff)
+            {
+                u64Diff = u32TillWrap;
+                pTimer->u8Wrap = 1;
+            }
         }
     }
@@ -349 +366 @@
 #endif
 
-    Log4(("HPET: next IRQ in %lld ticks (%lld ns)\n", u64Diff, hpetTicksToNs(u64Diff)));
-
-    TMTimerSetNano(pTimer->CTX_SUFF(pTimer), hpetTicksToNs(u64Diff));
+    Log4(("HPET: next IRQ in %lld ticks (%lld ns)\n", u64Diff, hpetTicksToNs(pTimer->CTX_SUFF(pHpet), u64Diff)));
+
+    TMTimerSetNano(pTimer->CTX_SUFF(pTimer), hpetTicksToNs(pTimer->CTX_SUFF(pHpet), u64Diff));
 }
 
@@ -410 +427 @@
         default:
             LogRel(("invalid HPET register read %d on %d\n", iTimerReg, pTimer->u8TimerNumber));
+            *pValue = 0;
             break;
         }
@@ -442 +460 @@
         {
             uint64_t u64Ticks;
-            Log(("read HPET_COUNTER\n"));
             if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
                 u64Ticks = hpetGetTicks(pThis);
@@ -449 +466 @@
             /** @todo: is it correct? */
             *pValue = (iIndex == HPET_COUNTER) ? (uint32_t)u64Ticks : (uint32_t)(u64Ticks >> 32);
+            Log(("read HPET_COUNTER: %s part value %x\n", (iIndex == HPET_COUNTER) ? "low" : "high", *pValue));
             break;
         }
@@ -457 +475 @@
         default:
             Log(("invalid HPET register read: %x\n", iIndex));
+            *pValue = 0;
             break;
     }
@@ -488 +507 @@
         case HPET_TN_CFG:
         {
-            Log(("write HPET_TN_CFG: %d\n", iTimerNo));
-            if (iNewValue & HPET_TN_32BIT)
-            {
+            Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, iNewValue));
+            if ((iNewValue & HPET_TN_32BIT) != 0)
+            {
+                Log(("setting timer to 32-bit mode\n"));
                 pTimer->u64Cmp = (uint32_t)pTimer->u64Cmp;
                 pTimer->u64Period = (uint32_t)pTimer->u64Period;
@@ -497 +517 @@
             {
                 LogRel(("level-triggered config not yet supported\n"));
-                Assert(false);
+                AssertFailed();
             }
             /** We only care about lower 32-bits so far */
@@ -574 +594 @@
         {
             LogRel(("invalid timer register write: %d\n", iTimerReg));
-            Assert(false);
+            AssertFailed();
             break;
         }
@@ -636 +656 @@
             {
                 /* Enable main counter and interrupt generation. */
-                pThis->u64HpetOffset = hpetTicksToNs(pThis->u64HpetCounter)
+                pThis->u64HpetOffset = hpetTicksToNs(pThis, pThis->u64HpetCounter)
                         - TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer));
                 for (i = 0; i < HPET_NUM_TIMERS; i++)
@@ -745 +765 @@
                 uint32_t iTimer = (iIndex - 0x100) / 0x20;
                 uint32_t iTimerReg = (iIndex - 0x100) % 0x20;
-                
+
                 /* for most 8-byte accesses we just split them, happens under lock anyway. */
                 rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg, &value.u32[0]);
@@ -756 +776 @@
                 if (iIndex == HPET_COUNTER)
                 {
-                    /* When reading HPET counter we must read it in a single read, 
+                    /* When reading HPET counter we must read it in a single read,
                        to avoid unexpected time jumps on 32-bit overflow. */
-                    value.u64 = 
-                            (pThis->u64HpetConfig & HPET_CFG_ENABLE) != 0 
+                    value.u64 =
+                            (pThis->u64HpetConfig & HPET_CFG_ENABLE) != 0
                             ?
                             hpetGetTicks(pThis)
@@ -769 +789 @@
                 {
                     /* for most 8-byte accesses we just split them, happens under lock anyway. */
-                    
+
                     rc = hpetConfigRegRead32(pThis, iIndex, &value.u32[0]);
                     if (RT_UNLIKELY(rc != VINF_SUCCESS))
@@ -1011 +1031 @@
             pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP);
         else
-            Assert(false);
+            AssertFailed();
         /* @todo: implement IRQs in level-triggered mode */
     }
@@ -1048 +1068 @@
         u64Diff = hpetComputeDiff(pTimer, u64CurTick);
 
-        Log4(("HPET: periodical: next in %lld\n",  hpetTicksToNs(u64Diff)));
-        TMTimerSetNano(pTmTimer, hpetTicksToNs(u64Diff));
+        Log4(("HPET: periodical: next in %lld\n",  hpetTicksToNs(pThis, u64Diff)));
+        TMTimerSetNano(pTmTimer, hpetTicksToNs(pThis, u64Diff));
     }
     else if ((pTimer->u64Config & HPET_TN_32BIT) &&
@@ -1057 +1077 @@
         {
             u64Diff = hpetComputeDiff(pTimer, u64CurTick);
-            TMTimerSetNano(pTmTimer, hpetTicksToNs(u64Diff));
+            TMTimerSetNano(pTmTimer, hpetTicksToNs(pThis, u64Diff));
             pTimer->u8Wrap = 0;
         }
@@ -1122 +1142 @@
     pThis->u64HpetCounter = 0ULL;
     pThis->u64HpetOffset = 0ULL;
+
+    uint32_t u32Vendor = 0x8086;
     /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
-    uint32_t u32Vendor = 0x8086;
     uint32_t u32Caps =
       (1 << 15) /* LEG_RT_CAP, LegacyReplacementRoute capable */ |
       (1 << 13) /* COUNTER_SIZE_CAP, main counter is 64-bit capable */ |
-      ((HPET_NUM_TIMERS-1) << 8) /* NUM_TIM_CAP, number of timers -1 */ |
+      /* Actually ICH9 has 4 timers, but to avoid breaking saved state we'll stick with 3 so far. */
+      (HPET_NUM_TIMERS << 8) /* NUM_TIM_CAP, number of timers -1 */ |
       1 /* REV_ID, revision, must not be 0 */;
     pThis->u64Capabilities = (u32Vendor << 16) | u32Caps;
-    pThis->u64Capabilities |= ((uint64_t)(HPET_CLK_PERIOD) << 32);
+    pThis->u64Capabilities |= ((uint64_t)(pThis->fIch9 ? HPET_CLK_PERIOD_ICH9 : HPET_CLK_PERIOD) << 32);
 
     /* Notify PIT/RTC devices */
@@ -1147 +1169 @@
     int        rc;
     HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
-
-    memset(pThis, 0, sizeof(*pThis));
 
     pThis->pDevInsR3 = pDevIns;
@@ -1218 +1238 @@
     bool         fRCEnabled = false;
     bool         fR0Enabled = false;
+    bool         fIch9      = false;
     PDMHPETREG   HpetReg;
 
-    /* Only one HPET device now */
+    /* Only one HPET device now, as we use fixed MMIO region. */
     Assert(iInstance == 0);
 
@@ -1226 +1247 @@
      * Validate configuration.
      */
-    if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
+    if (!CFGMR3AreValuesValid(pCfg,
+                              "GCEnabled\0"
+                              "R0Enabled\0"
+                              "ICH9\0"))
         return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
 
@@ -1239 +1263 @@
         return PDMDEV_SET_ERROR(pDevIns, rc,
                                 N_("Configuration error: failed to read R0Enabled as boolean"));
+    rc = CFGMR3QueryBoolDef(pCfg, "ICH9", &fIch9, false);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("Configuration error: failed to read ICH9 as boolean"));
+
     /* Initialize the device state */
+    memset(pThis, 0, sizeof(*pThis));
+
+    pThis->fIch9 = (uint8_t)fIch9;
+
     rc = hpetInit(pDevIns);
     if (RT_FAILURE(rc))

trunk/src/VBox/Main/src-client/ConsoleImpl2.cpp

@@ -1072 +1072 @@
             InsertConfigNode(pDev,     "0", &pInst);
             InsertConfigInteger(pInst, "Trusted",   1); /* boolean */
+            InsertConfigNode(pInst,    "Config", &pCfg);
+            InsertConfigInteger(pCfg,  "ICH9", (chipsetType == ChipsetType_ICH9) ? 1 : 0);  /* boolean */
         }