Changeset 3696 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Jul 18, 2007 5:00:33 PM (18 years ago)
- svn:sync-xref-src-repo-rev:
- 22987
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 4 edited
-
CPUMAllA.asm (modified) (8 diffs)
-
EMAllA.asm (modified) (32 diffs)
-
PGMAll.cpp (modified) (2 diffs)
-
TMAllVirtual.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm
r2988 r3696 40 40 ;; @def CPUM_REG 41 41 ; The register which we load the CPUM pointer into. 42 %ifdef __AMD64__42 %ifdef RT_ARCH_AMD64 43 43 %define CPUM_REG rdx 44 44 %else … … 95 95 ; loaded the GC FPU. Because if we have, this is an trap for the guest - raw ring-3. 96 96 ; 97 %ifdef __AMD64__98 %ifdef __WIN__97 %ifdef RT_ARCH_AMD64 98 %ifdef RT_OS_WINDOWS 99 99 mov xDX, rcx 100 100 %else … … 115 115 mov eax, [xDX + CPUM.Guest.cr0] 116 116 and eax, X86_CR0_MP | X86_CR0_EM | X86_CR0_TS 117 %ifdef __AMD64__117 %ifdef RT_ARCH_AMD64 118 118 lea r8, [hlfpuajmp1 wrt rip] 119 119 jmp qword [rax*4 + r8] … … 150 150 %ifndef IN_RING3 ; IN_GC or IN_RING0 151 151 mov xCX, cr0 152 %ifdef __AMD64__152 %ifdef RT_ARCH_AMD64 153 153 lea r8, [hlfpu_afFlags wrt rip] 154 154 and rcx, [rax*4 + r8] ; calc the new cr0 flags. … … 160 160 mov cr0, xAX ; clear flags so we don't trap here. 161 161 %endif 162 %ifndef __AMD64__162 %ifndef RT_ARCH_AMD64 163 163 test dword [xDX + CPUM.CPUFeatures.edx], X86_CPUID_FEATURE_EDX_FXSR 164 164 jz short hlfpua_no_fxsave … … 176 176 ret 177 177 178 %ifndef __AMD64__178 %ifndef RT_ARCH_AMD64 179 179 ; legacy support. 180 180 hlfpua_no_fxsave: … … 191 191 frstor [xDX + CPUM.Guest.fpu] 192 192 jmp near hlfpua_finished_switch 193 %endif ; ! __AMD64__193 %endif ; !RT_ARCH_AMD64 194 194 195 195 … … 212 212 align 16 213 213 BEGINPROC CPUMRestoreHostFPUStateAsm 214 %ifdef __AMD64__215 %ifdef __WIN__214 %ifdef RT_ARCH_AMD64 215 %ifdef RT_OS_WINDOWS 216 216 mov xDX, rcx 217 217 %else -
trunk/src/VBox/VMM/VMMAll/EMAllA.asm
r2988 r3696 29 29 ;; @def MY_PTR_REG 30 30 ; The register we use for value pointers (And,Or,Dec,Inc). 31 %ifdef __AMD64__31 %ifdef RT_ARCH_AMD64 32 32 %define MY_PTR_REG rcx 33 33 %else … … 37 37 ;; @def MY_RET_REG 38 38 ; The register we return the result in. 39 %ifdef __AMD64__39 %ifdef RT_ARCH_AMD64 40 40 %define MY_RET_REG rax 41 41 %else … … 57 57 align 16 58 58 BEGINPROC EMEmulateCmp 59 %ifdef __AMD64__59 %ifdef RT_ARCH_AMD64 60 60 %ifdef __WIN64__ 61 61 mov rax, r8 ; eax = size of parameters … … 65 65 mov rdx, rsi ; rdx = second parameter 66 66 %endif ; !__WIN64__ 67 %else ; ! __AMD64__67 %else ; !RT_ARCH_AMD64 68 68 mov eax, [esp + 0ch] ; eax = size of parameters 69 69 mov ecx, [esp + 04h] ; ecx = first parameter … … 72 72 73 73 ; switch on size 74 %ifdef __AMD64__75 cmp al, 8 76 je short .do_qword ; 8 bytes variant 77 %endif 78 cmp al, 4 79 je short .do_dword ; 4 bytes variant 80 cmp al, 2 81 je short .do_word ; 2 byte variant 82 cmp al, 1 83 je short .do_byte ; 1 bytes variant 84 int3 85 86 ; workers 87 %ifdef __AMD64__74 %ifdef RT_ARCH_AMD64 75 cmp al, 8 76 je short .do_qword ; 8 bytes variant 77 %endif 78 cmp al, 4 79 je short .do_dword ; 4 bytes variant 80 cmp al, 2 81 je short .do_word ; 2 byte variant 82 cmp al, 1 83 je short .do_byte ; 1 bytes variant 84 int3 85 86 ; workers 87 %ifdef RT_ARCH_AMD64 88 88 .do_qword: 89 89 cmp rcx, rdx ; do 8 bytes CMP … … 122 122 align 16 123 123 BEGINPROC EMEmulateAnd 124 %ifdef __AMD64__124 %ifdef RT_ARCH_AMD64 125 125 %ifdef __WIN64__ 126 126 mov rax, r8 ; eax = size of parameters … … 130 130 mov rdx, rsi ; rdx = second parameter 131 131 %endif ; !__WIN64__ 132 %else ; ! __AMD64__132 %else ; !RT_ARCH_AMD64 133 133 mov eax, [esp + 0ch] ; eax = size of parameters 134 134 mov ecx, [esp + 04h] ; ecx = first parameter … … 137 137 138 138 ; switch on size 139 %ifdef __AMD64__140 cmp al, 8 141 je short .do_qword ; 8 bytes variant 142 %endif 143 cmp al, 4 144 je short .do_dword ; 4 bytes variant 145 cmp al, 2 146 je short .do_word ; 2 byte variant 147 cmp al, 1 148 je short .do_byte ; 1 bytes variant 149 int3 150 151 ; workers 152 %ifdef __AMD64__139 %ifdef RT_ARCH_AMD64 140 cmp al, 8 141 je short .do_qword ; 8 bytes variant 142 %endif 143 cmp al, 4 144 je short .do_dword ; 4 bytes variant 145 cmp al, 2 146 je short .do_word ; 2 byte variant 147 cmp al, 1 148 je short .do_byte ; 1 bytes variant 149 int3 150 151 ; workers 152 %ifdef RT_ARCH_AMD64 153 153 .do_qword: 154 154 and [MY_PTR_REG], rdx ; do 8 bytes AND … … 187 187 align 16 188 188 BEGINPROC EMEmulateOr 189 %ifdef __AMD64__189 %ifdef RT_ARCH_AMD64 190 190 %ifdef __WIN64__ 191 191 mov rax, r8 ; eax = size of parameters … … 195 195 mov rdx, rsi ; rdx = second parameter 196 196 %endif ; !__WIN64__ 197 %else ; ! __AMD64__197 %else ; !RT_ARCH_AMD64 198 198 mov eax, [esp + 0ch] ; eax = size of parameters 199 199 mov ecx, [esp + 04h] ; ecx = first parameter … … 202 202 203 203 ; switch on size 204 %ifdef __AMD64__205 cmp al, 8 206 je short .do_qword ; 8 bytes variant 207 %endif 208 cmp al, 4 209 je short .do_dword ; 4 bytes variant 210 cmp al, 2 211 je short .do_word ; 2 byte variant 212 cmp al, 1 213 je short .do_byte ; 1 bytes variant 214 int3 215 216 ; workers 217 %ifdef __AMD64__204 %ifdef RT_ARCH_AMD64 205 cmp al, 8 206 je short .do_qword ; 8 bytes variant 207 %endif 208 cmp al, 4 209 je short .do_dword ; 4 bytes variant 210 cmp al, 2 211 je short .do_word ; 2 byte variant 212 cmp al, 1 213 je short .do_byte ; 1 bytes variant 214 int3 215 216 ; workers 217 %ifdef RT_ARCH_AMD64 218 218 .do_qword: 219 219 or [MY_PTR_REG], rdx ; do 8 bytes OR … … 251 251 align 16 252 252 BEGINPROC EMEmulateXor 253 %ifdef __AMD64__253 %ifdef RT_ARCH_AMD64 254 254 %ifdef __WIN64__ 255 255 mov rax, r8 ; eax = size of parameters … … 259 259 mov rdx, rsi ; rdx = second parameter 260 260 %endif ; !__WIN64__ 261 %else ; ! __AMD64__261 %else ; !RT_ARCH_AMD64 262 262 mov eax, [esp + 0ch] ; eax = size of parameters 263 263 mov ecx, [esp + 04h] ; ecx = first parameter … … 266 266 267 267 ; switch on size 268 %ifdef __AMD64__269 cmp al, 8 270 je short .do_qword ; 8 bytes variant 271 %endif 272 cmp al, 4 273 je short .do_dword ; 4 bytes variant 274 cmp al, 2 275 je short .do_word ; 2 byte variant 276 cmp al, 1 277 je short .do_byte ; 1 bytes variant 278 int3 279 280 ; workers 281 %ifdef __AMD64__268 %ifdef RT_ARCH_AMD64 269 cmp al, 8 270 je short .do_qword ; 8 bytes variant 271 %endif 272 cmp al, 4 273 je short .do_dword ; 4 bytes variant 274 cmp al, 2 275 je short .do_word ; 2 byte variant 276 cmp al, 1 277 je short .do_byte ; 1 bytes variant 278 int3 279 280 ; workers 281 %ifdef RT_ARCH_AMD64 282 282 .do_qword: 283 283 xor [MY_PTR_REG], rdx ; do 8 bytes XOR … … 314 314 align 16 315 315 BEGINPROC EMEmulateInc 316 %ifdef __AMD64__316 %ifdef RT_ARCH_AMD64 317 317 %ifdef __WIN64__ 318 318 mov rax, rdx ; eax = size of parameters … … 321 321 mov rcx, rdi ; rcx = first parameter 322 322 %endif ; !__WIN64__ 323 %else ; ! __AMD64__323 %else ; !RT_ARCH_AMD64 324 324 mov eax, [esp + 08h] ; eax = size of parameters 325 325 mov ecx, [esp + 04h] ; ecx = first parameter … … 327 327 328 328 ; switch on size 329 %ifdef __AMD64__330 cmp al, 8 331 je short .do_qword ; 8 bytes variant 332 %endif 333 cmp al, 4 334 je short .do_dword ; 4 bytes variant 335 cmp al, 2 336 je short .do_word ; 2 byte variant 337 cmp al, 1 338 je short .do_byte ; 1 bytes variant 339 int3 340 341 ; workers 342 %ifdef __AMD64__329 %ifdef RT_ARCH_AMD64 330 cmp al, 8 331 je short .do_qword ; 8 bytes variant 332 %endif 333 cmp al, 4 334 je short .do_dword ; 4 bytes variant 335 cmp al, 2 336 je short .do_word ; 2 byte variant 337 cmp al, 1 338 je short .do_byte ; 1 bytes variant 339 int3 340 341 ; workers 342 %ifdef RT_ARCH_AMD64 343 343 .do_qword: 344 344 inc qword [MY_PTR_REG] ; do 8 bytes INC … … 377 377 align 16 378 378 BEGINPROC EMEmulateDec 379 %ifdef __AMD64__379 %ifdef RT_ARCH_AMD64 380 380 %ifdef __WIN64__ 381 381 mov rax, rdx ; eax = size of parameters … … 384 384 mov rcx, rdi ; rcx = first parameter 385 385 %endif ; !__WIN64__ 386 %else ; ! __AMD64__386 %else ; !RT_ARCH_AMD64 387 387 mov eax, [esp + 08h] ; eax = size of parameters 388 388 mov ecx, [esp + 04h] ; ecx = first parameter … … 390 390 391 391 ; switch on size 392 %ifdef __AMD64__393 cmp al, 8 394 je short .do_qword ; 8 bytes variant 395 %endif 396 cmp al, 4 397 je short .do_dword ; 4 bytes variant 398 cmp al, 2 399 je short .do_word ; 2 byte variant 400 cmp al, 1 401 je short .do_byte ; 1 bytes variant 402 int3 403 404 ; workers 405 %ifdef __AMD64__392 %ifdef RT_ARCH_AMD64 393 cmp al, 8 394 je short .do_qword ; 8 bytes variant 395 %endif 396 cmp al, 4 397 je short .do_dword ; 4 bytes variant 398 cmp al, 2 399 je short .do_word ; 2 byte variant 400 cmp al, 1 401 je short .do_byte ; 1 bytes variant 402 int3 403 404 ; workers 405 %ifdef RT_ARCH_AMD64 406 406 .do_qword: 407 407 dec qword [MY_PTR_REG] ; do 8 bytes DEC … … 440 440 align 16 441 441 BEGINPROC EMEmulateAdd 442 %ifdef __AMD64__442 %ifdef RT_ARCH_AMD64 443 443 %ifdef __WIN64__ 444 444 mov rax, r8 ; eax = size of parameters … … 448 448 mov rdx, rsi ; rdx = second parameter 449 449 %endif ; !__WIN64__ 450 %else ; ! __AMD64__450 %else ; !RT_ARCH_AMD64 451 451 mov eax, [esp + 0ch] ; eax = size of parameters 452 452 mov ecx, [esp + 04h] ; ecx = first parameter … … 455 455 456 456 ; switch on size 457 %ifdef __AMD64__458 cmp al, 8 459 je short .do_qword ; 8 bytes variant 460 %endif 461 cmp al, 4 462 je short .do_dword ; 4 bytes variant 463 cmp al, 2 464 je short .do_word ; 2 byte variant 465 cmp al, 1 466 je short .do_byte ; 1 bytes variant 467 int3 468 469 ; workers 470 %ifdef __AMD64__457 %ifdef RT_ARCH_AMD64 458 cmp al, 8 459 je short .do_qword ; 8 bytes variant 460 %endif 461 cmp al, 4 462 je short .do_dword ; 4 bytes variant 463 cmp al, 2 464 je short .do_word ; 2 byte variant 465 cmp al, 1 466 je short .do_byte ; 1 bytes variant 467 int3 468 469 ; workers 470 %ifdef RT_ARCH_AMD64 471 471 .do_qword: 472 472 add [MY_PTR_REG], rdx ; do 8 bytes ADD … … 504 504 align 16 505 505 BEGINPROC EMEmulateAdcWithCarrySet 506 %ifdef __AMD64__506 %ifdef RT_ARCH_AMD64 507 507 %ifdef __WIN64__ 508 508 mov rax, r8 ; eax = size of parameters … … 512 512 mov rdx, rsi ; rdx = second parameter 513 513 %endif ; !__WIN64__ 514 %else ; ! __AMD64__514 %else ; !RT_ARCH_AMD64 515 515 mov eax, [esp + 0ch] ; eax = size of parameters 516 516 mov ecx, [esp + 04h] ; ecx = first parameter … … 519 519 520 520 ; switch on size 521 %ifdef __AMD64__522 cmp al, 8 523 je short .do_qword ; 8 bytes variant 524 %endif 525 cmp al, 4 526 je short .do_dword ; 4 bytes variant 527 cmp al, 2 528 je short .do_word ; 2 byte variant 529 cmp al, 1 530 je short .do_byte ; 1 bytes variant 531 int3 532 533 ; workers 534 %ifdef __AMD64__521 %ifdef RT_ARCH_AMD64 522 cmp al, 8 523 je short .do_qword ; 8 bytes variant 524 %endif 525 cmp al, 4 526 je short .do_dword ; 4 bytes variant 527 cmp al, 2 528 je short .do_word ; 2 byte variant 529 cmp al, 1 530 je short .do_byte ; 1 bytes variant 531 int3 532 533 ; workers 534 %ifdef RT_ARCH_AMD64 535 535 .do_qword: 536 536 stc ; set carry flag … … 572 572 align 16 573 573 BEGINPROC EMEmulateSub 574 %ifdef __AMD64__574 %ifdef RT_ARCH_AMD64 575 575 %ifdef __WIN64__ 576 576 mov rax, r8 ; eax = size of parameters … … 580 580 mov rdx, rsi ; rdx = second parameter 581 581 %endif ; !__WIN64__ 582 %else ; ! __AMD64__582 %else ; !RT_ARCH_AMD64 583 583 mov eax, [esp + 0ch] ; eax = size of parameters 584 584 mov ecx, [esp + 04h] ; ecx = first parameter … … 587 587 588 588 ; switch on size 589 %ifdef __AMD64__590 cmp al, 8 591 je short .do_qword ; 8 bytes variant 592 %endif 593 cmp al, 4 594 je short .do_dword ; 4 bytes variant 595 cmp al, 2 596 je short .do_word ; 2 byte variant 597 cmp al, 1 598 je short .do_byte ; 1 bytes variant 599 int3 600 601 ; workers 602 %ifdef __AMD64__589 %ifdef RT_ARCH_AMD64 590 cmp al, 8 591 je short .do_qword ; 8 bytes variant 592 %endif 593 cmp al, 4 594 je short .do_dword ; 4 bytes variant 595 cmp al, 2 596 je short .do_word ; 2 byte variant 597 cmp al, 1 598 je short .do_byte ; 1 bytes variant 599 int3 600 601 ; workers 602 %ifdef RT_ARCH_AMD64 603 603 .do_qword: 604 604 sub [MY_PTR_REG], rdx ; do 8 bytes SUB … … 636 636 align 16 637 637 BEGINPROC EMEmulateBtr 638 %ifdef __AMD64__638 %ifdef RT_ARCH_AMD64 639 639 %ifndef __WIN64__ 640 640 mov rcx, rdi ; rcx = first parameter 641 641 mov rdx, rsi ; rdx = second parameter 642 642 %endif ; !__WIN64__ 643 %else ; ! __AMD64__643 %else ; !RT_ARCH_AMD64 644 644 mov ecx, [esp + 04h] ; ecx = first parameter 645 645 mov edx, [esp + 08h] ; edx = second parameter … … 666 666 align 16 667 667 BEGINPROC EMEmulateBtc 668 %ifdef __AMD64__668 %ifdef RT_ARCH_AMD64 669 669 %ifndef __WIN64__ 670 670 mov rcx, rdi ; rcx = first parameter 671 671 mov rdx, rsi ; rdx = second parameter 672 672 %endif ; !__WIN64__ 673 %else ; ! __AMD64__673 %else ; !RT_ARCH_AMD64 674 674 mov ecx, [esp + 04h] ; ecx = first parameter 675 675 mov edx, [esp + 08h] ; edx = second parameter … … 696 696 align 16 697 697 BEGINPROC EMEmulateBts 698 %ifdef __AMD64__698 %ifdef RT_ARCH_AMD64 699 699 %ifndef __WIN64__ 700 700 mov rcx, rdi ; rcx = first parameter 701 701 mov rdx, rsi ; rdx = second parameter 702 702 %endif ; !__WIN64__ 703 %else ; ! __AMD64__703 %else ; !RT_ARCH_AMD64 704 704 mov ecx, [esp + 04h] ; ecx = first parameter 705 705 mov edx, [esp + 08h] ; edx = second parameter -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r2981 r3696 84 84 85 85 86 #if 1///@todo ndef __AMD64__86 #if 1///@todo ndef RT_ARCH_AMD64 87 87 /* 88 88 * Shadow - 32-bit mode … … 132 132 #undef PGM_SHW_TYPE 133 133 #undef PGM_SHW_NAME 134 #endif /* ! __AMD64__*/134 #endif /* !RT_ARCH_AMD64 */ 135 135 136 136 -
trunk/src/VBox/VMM/VMMAll/TMAllVirtual.cpp
r3393 r3696 137 137 u64Delta = u32UpdateIntervalTSC; 138 138 } 139 #if !defined(_MSC_VER) || defined( __AMD64__) /* GCC makes very pretty code from these two inline calls, while MSC cannot. */139 #if !defined(_MSC_VER) || defined(RT_ARCH_AMD64) /* GCC makes very pretty code from these two inline calls, while MSC cannot. */ 140 140 u64Delta = ASMMult2xU32RetU64((uint32_t)u64Delta, u32NanoTSFactor0); 141 141 u64Delta = ASMDivU64ByU32RetU32(u64Delta, u32UpdateIntervalTSC);
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