VirtualBox

Changeset 37323 in vbox for trunk/src/VBox/VMM/VMMR0


Ignore:
Timestamp:
Jun 3, 2011 4:20:06 PM (14 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
72078
Message:

build fix and some prefix cleanup.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r37320 r37323  
    179179    {
    180180        /* Allocate one page for the APIC physical page (serves for filtering accesses). */
    181         rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
     181        rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, PAGE_SIZE, true /* executable R0 mapping */);
    182182        AssertRC(rc);
    183183        if (RT_FAILURE(rc))
    … …  
    197197#ifdef VBOX_WITH_CRASHDUMP_MAGIC
    198198    {
    199         rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
     199        rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, PAGE_SIZE, true /* executable R0 mapping */);
    200200        AssertRC(rc);
    201201        if (RT_FAILURE(rc))
    … …  
    216216        PVMCPU pVCpu = &pVM->aCpus[i];
    217217
    218         pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
     218        pVCpu->hwaccm.s.vmx.hMemObjVMCS = NIL_RTR0MEMOBJ;
    219219
    220220        /* Allocate one page for the VM control structure (VMCS). */
    221         rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
     221        rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.hMemObjVMCS, PAGE_SIZE, true /* executable R0 mapping */);
    222222        AssertRC(rc);
    223223        if (RT_FAILURE(rc))
    224224            return rc;
    225225
    226         pVCpu->hwaccm.s.vmx.pVMCS     = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
    227         pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
    228         ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
     226        pVCpu->hwaccm.s.vmx.pvVMCS     = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.hMemObjVMCS);
     227        pVCpu->hwaccm.s.vmx.HCPhysVMCS = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.hMemObjVMCS, 0);
     228        ASMMemZeroPage(pVCpu->hwaccm.s.vmx.pvVMCS);
    229229
    230230        pVCpu->hwaccm.s.vmx.cr0_mask = 0;
    … …  
    232232
    233233        /* Allocate one page for the virtual APIC page for TPR caching. */
    234         rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
     234        rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.hMemObjVAPIC, PAGE_SIZE, true /* executable R0 mapping */);
    235235        AssertRC(rc);
    236236        if (RT_FAILURE(rc))
    237237            return rc;
    238238
    239         pVCpu->hwaccm.s.vmx.pVAPIC     = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
    240         pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
    241         ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
     239        pVCpu->hwaccm.s.vmx.pbVAPIC     = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.hMemObjVAPIC);
     240        pVCpu->hwaccm.s.vmx.HCPhysVAPIC = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.hMemObjVAPIC, 0);
     241        ASMMemZeroPage(pVCpu->hwaccm.s.vmx.pbVAPIC);
    242242
    243243        /* Allocate the MSR bitmap if this feature is supported. */
    244244        if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
    245245        {
    246             rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
     246            rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap, PAGE_SIZE, true /* executable R0 mapping */);
    247247            AssertRC(rc);
    248248            if (RT_FAILURE(rc))
    … …  
    256256#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
    257257        /* Allocate one page for the guest MSR load area (for preloading guest MSRs during the world switch). */
    258         rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjGuestMSR, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
     258        rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjGuestMSR, PAGE_SIZE, true /* executable R0 mapping */);
    259259        AssertRC(rc);
    260260        if (RT_FAILURE(rc))
    … …  
    266266
    267267        /* Allocate one page for the host MSR load area (for restoring host MSRs after the world switch back). */
    268         rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjHostMSR, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
     268        rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjHostMSR, PAGE_SIZE, true /* executable R0 mapping */);
    269269        AssertRC(rc);
    270270        if (RT_FAILURE(rc))
    … …  
    280280
    281281#ifdef LOG_ENABLED
    282         SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
     282        SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pvVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    283283#endif
    284284    }
    … …  
    299299        PVMCPU pVCpu = &pVM->aCpus[i];
    300300
    301         if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
    302         {
    303             RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
    304             pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
    305             pVCpu->hwaccm.s.vmx.pVMCS       = 0;
    306             pVCpu->hwaccm.s.vmx.pVMCSPhys   = 0;
    307         }
    308         if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
    309         {
    310             RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
    311             pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
    312             pVCpu->hwaccm.s.vmx.pVAPIC       = 0;
    313             pVCpu->hwaccm.s.vmx.pVAPICPhys   = 0;
     301        if (pVCpu->hwaccm.s.vmx.hMemObjVMCS != NIL_RTR0MEMOBJ)
     302        {
     303            RTR0MemObjFree(pVCpu->hwaccm.s.vmx.hMemObjVMCS, false);
     304            pVCpu->hwaccm.s.vmx.hMemObjVMCS = NIL_RTR0MEMOBJ;
     305            pVCpu->hwaccm.s.vmx.pvVMCS      = 0;
     306            pVCpu->hwaccm.s.vmx.HCPhysVMCS  = 0;
     307        }
     308        if (pVCpu->hwaccm.s.vmx.hMemObjVAPIC != NIL_RTR0MEMOBJ)
     309        {
     310            RTR0MemObjFree(pVCpu->hwaccm.s.vmx.hMemObjVAPIC, false);
     311            pVCpu->hwaccm.s.vmx.hMemObjVAPIC = NIL_RTR0MEMOBJ;
     312            pVCpu->hwaccm.s.vmx.pbVAPIC      = 0;
     313            pVCpu->hwaccm.s.vmx.HCPhysVAPIC  = 0;
    314314        }
    315315        if (pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
    … …  
    374374        PVMCPU pVCpu = &pVM->aCpus[i];
    375375
    376         Assert(pVCpu->hwaccm.s.vmx.pVMCS);
     376        AssertPtr(pVCpu->hwaccm.s.vmx.pvVMCS);
    377377
    378378        /* Set revision dword at the beginning of the VMCS structure. */
    379         *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
     379        *(uint32_t *)pVCpu->hwaccm.s.vmx.pvVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
    380380
    381381        /* Clear VM Control Structure. */
    382         Log(("pVMCSPhys  = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
    383         rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
     382        Log(("HCPhysVMCS  = %RHp\n", pVCpu->hwaccm.s.vmx.HCPhysVMCS));
     383        rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    384384        if (RT_FAILURE(rc))
    385385            goto vmx_end;
    386386
    387387        /* Activate the VM Control Structure. */
    388         rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
     388        rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    389389        if (RT_FAILURE(rc))
    390390            goto vmx_end;
    … …  
    561561            /* Optional */
    562562            rc  = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
    563             rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
     563            rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.HCPhysVAPIC);
    564564
    565565            if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
    … …  
    574574
    575575        /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
    576         rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
     576        rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    577577        AssertRC(rc);
    578578
    … …  
    23202320#endif
    23212321
    2322     Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
     2322    Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pbVAPIC && pVM->hwaccm.s.vmx.pAPIC));
    23232323
    23242324    /* Check if we need to use TPR shadowing. */
    … …  
    25512551        AssertRC(rc2);
    25522552        /* The TPR can be found at offset 0x80 in the APIC mmio page. */
    2553         pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
     2553        pVCpu->hwaccm.s.vmx.pbVAPIC[0x80] = u8LastTPR;
    25542554
    25552555        /* Two options here:
    … …  
    27172717    {
    27182718        Assert(pVM->hwaccm.s.fTPRPatchingActive);
    2719         pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
     2719        pVCpu->hwaccm.s.vmx.pbVAPIC[0x80] = pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
    27202720        ASMWrMsr(MSR_K8_LSTAR, u64OldLSTAR);
    27212721    }
    … …  
    28172817    /* Sync back the TPR if it was changed. */
    28182818    if (    fSetupTPRCaching
    2819         &&  u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
    2820     {
    2821         rc2 = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
     2819        &&  u8LastTPR != pVCpu->hwaccm.s.vmx.pbVAPIC[0x80])
     2820    {
     2821        rc2 = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pbVAPIC[0x80]);
    28222822        AssertRC(rc2);
    28232823    }
    … …  
    42364236    {
    42374237        VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
    4238         pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
     4238        pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pvVMCS;
    42394239        pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu   = pVCpu->hwaccm.s.idEnteredCpu;
    42404240        pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu   = RTMpCpuId();
    … …  
    42784278
    42794279    /* Activate the VM Control Structure. */
    4280     int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
     4280    int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    42814281    if (RT_FAILURE(rc))
    42824282        return rc;
    … …  
    43244324
    43254325    /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
    4326     int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
     4326    int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    43274327    AssertRC(rc);
    43284328
    … …  
    46304630#ifdef DEBUG
    46314631    pCache->TestIn.HCPhysCpuPage= 0;
    4632     pCache->TestIn.pVMCSPhys    = 0;
     4632    pCache->TestIn.HCPhysVMCS   = 0;
    46334633    pCache->TestIn.pCache       = 0;
    4634     pCache->TestOut.pVMCSPhys   = 0;
     4634    pCache->TestOut.HCPhysVMCS  = 0;
    46354635    pCache->TestOut.pCache      = 0;
    46364636    pCache->TestOut.pCtx        = 0;
    … …  
    46404640    aParam[0] = (uint32_t)(HCPhysCpuPage);                                  /* Param 1: VMXON physical address - Lo. */
    46414641    aParam[1] = (uint32_t)(HCPhysCpuPage >> 32);                            /* Param 1: VMXON physical address - Hi. */
    4642     aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys);                  /* Param 2: VMCS physical address - Lo. */
    4643     aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32);            /* Param 2: VMCS physical address - Hi. */
     4642    aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.HCPhysVMCS);                 /* Param 2: VMCS physical address - Lo. */
     4643    aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.HCPhysVMCS >> 32);           /* Param 2: VMCS physical address - Hi. */
    46444644    aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
    46454645    aParam[5] = 0;
    … …  
    46594659#ifdef DEBUG
    46604660    AssertMsg(pCache->TestIn.HCPhysCpuPage== HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
    4661     AssertMsg(pCache->TestIn.pVMCSPhys    == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
    4662     AssertMsg(pCache->TestIn.pVMCSPhys    == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
     4661    AssertMsg(pCache->TestIn.HCPhysVMCS   == pVCpu->hwaccm.s.vmx.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS, pVCpu->hwaccm.s.vmx.HCPhysVMCS));
     4662    AssertMsg(pCache->TestIn.HCPhysVMCS   == pCache->TestOut.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS, pCache->TestOut.HCPhysVMCS));
    46634663    AssertMsg(pCache->TestIn.pCache       == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
    46644664    AssertMsg(pCache->TestIn.pCache       == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
    … …  
    47074707
    47084708    /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
    4709     VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
     4709    VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    47104710
    47114711    /* Leave VMX Root Mode. */
    … …  
    47364736    }
    47374737
    4738     rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
     4738    rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
    47394739    AssertRC(rc2);
    47404740    Assert(!(ASMGetFlags() & X86_EFL_IF));
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