Changeset 37354 in vbox for trunk/src/VBox/VMM/VMMR3
- Timestamp:
- Jun 7, 2011 3:05:32 PM (14 years ago)
- Location:
- trunk/src/VBox/VMM/VMMR3
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/PGM.cpp
r36893 r37354 1327 1327 1328 1328 PGMR3PhysChunkInvalidateTLB(pVM); 1329 PGMPhysInvalidatePageMapTLB(pVM);1329 pgmPhysInvalidatePageMapTLB(pVM); 1330 1330 1331 1331 /* -
trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp
r37137 r37354 884 884 static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType) 885 885 { 886 Assert(PGMIsLockOwner(pVM));886 PGM_LOCK_ASSERT_OWNER(pVM); 887 887 uint32_t cPendingPages = 0; 888 888 PGMMFREEPAGESREQ pReq; … … 898 898 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */ 899 899 900 PGM_PAGE_SET_TYPE(p PageDst, uType);900 PGM_PAGE_SET_TYPE(pVM, pPageDst, uType); 901 901 902 902 GCPhys += PAGE_SIZE; … … 977 977 } 978 978 Assert(PGM_PAGE_IS_ZERO(pPage)); 979 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_BALLOONED);979 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED); 980 980 } 981 981 … … 1005 1005 1006 1006 /* Change back to zero page. */ 1007 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ZERO);1007 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO); 1008 1008 } 1009 1009 … … 1153 1153 if (PGM_PAGE_IS_WRITTEN_TO(pPage)) 1154 1154 { 1155 PGM_PAGE_CLEAR_WRITTEN_TO(p Page);1155 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage); 1156 1156 /* Remember this dirty page for the next (memory) sync. */ 1157 1157 PGM_PAGE_SET_FT_DIRTY(pPage); … … 1715 1715 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev); 1716 1716 } 1717 PGMPhysInvalidatePageMapTLB(pVM);1717 pgmPhysInvalidatePageMapTLB(pVM); 1718 1718 pgmUnlock(pVM); 1719 1719 … … 1806 1806 int pgmR3PhysRamReset(PVM pVM) 1807 1807 { 1808 Assert(PGMIsLockOwner(pVM));1808 PGM_LOCK_ASSERT_OWNER(pVM); 1809 1809 1810 1810 /* Reset the memory balloon. */ … … 1860 1860 { 1861 1861 /* Turn into a zero page; the balloon status is lost when the VM reboots. */ 1862 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ZERO);1862 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO); 1863 1863 } 1864 1864 else if (!PGM_PAGE_IS_ZERO(pPage)) … … 1900 1900 case PGM_PAGE_STATE_BALLOONED: 1901 1901 /* Turn into a zero page; the balloon status is lost when the VM reboots. */ 1902 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ZERO);1902 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO); 1903 1903 break; 1904 1904 … … 1962 1962 int pgmR3PhysRamTerm(PVM pVM) 1963 1963 { 1964 Assert(PGMIsLockOwner(pVM));1964 PGM_LOCK_ASSERT_OWNER(pVM); 1965 1965 1966 1966 /* Reset the memory balloon. */ … … 2065 2065 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER); 2066 2066 2067 int rc = pgmLock(pVM); 2068 AssertRCReturn(rc, rc); 2069 2067 2070 /* 2068 2071 * Make sure there's a RAM range structure for the region. 2069 2072 */ 2070 int rc;2071 2073 RTGCPHYS GCPhysLast = GCPhys + (cb - 1); 2072 2074 bool fRamExists = false; … … 2079 2081 { 2080 2082 /* Simplification: all within the same range. */ 2081 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys 2082 && GCPhysLast <= pRam->GCPhysLast, 2083 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n", 2084 GCPhys, GCPhysLast, pszDesc, 2085 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc), 2086 VERR_PGM_RAM_CONFLICT); 2083 AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys 2084 && GCPhysLast <= pRam->GCPhysLast, 2085 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n", 2086 GCPhys, GCPhysLast, pszDesc, 2087 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc), 2088 pgmUnlock(pVM), 2089 VERR_PGM_RAM_CONFLICT); 2087 2090 2088 2091 /* Check that it's all RAM or MMIO pages. */ … … 2091 2094 while (cLeft-- > 0) 2092 2095 { 2093 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM 2094 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO, 2095 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n", 2096 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc), 2097 VERR_PGM_RAM_CONFLICT); 2096 AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM 2097 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO, 2098 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n", 2099 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc), 2100 pgmUnlock(pVM), 2101 VERR_PGM_RAM_CONFLICT); 2098 2102 pPage++; 2099 2103 } … … 2118 2122 * for PCI memory, but we're doing the same thing for MMIO2 pages. 2119 2123 */ 2120 rc = pgmLock(pVM); 2121 if (RT_SUCCESS(rc)) 2122 { 2123 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO); 2124 pgmUnlock(pVM); 2125 } 2126 AssertRCReturn(rc, rc); 2124 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO); 2125 AssertRCReturnStmt(rc, pgmUnlock(pVM), rc); 2127 2126 2128 2127 /* Force a PGM pool flush as guest ram references have been changed. */ 2129 /** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */ 2128 /** @todo not entirely SMP safe; assuming for now the guest takes 2129 * care of this internally (not touch mapped mmio while changing the 2130 * mapping). */ 2130 2131 PVMCPU pVCpu = VMMGetCpu(pVM); 2131 2132 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL; … … 2134 2135 else 2135 2136 { 2136 pgmLock(pVM);2137 2137 2138 2138 /* … … 2147 2147 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]); 2148 2148 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew); 2149 AssertLogRelMsgRCReturn (rc, ("cbRamRange=%zu\n", cbRamRange), rc);2149 AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), pgmUnlock(pVM), rc); 2150 2150 2151 2151 /* Initialize the range. */ … … 2171 2171 /* link it */ 2172 2172 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev); 2173 2174 pgmUnlock(pVM);2175 2173 } 2176 2174 … … 2193 2191 MMHyperFree(pVM, pRam); 2194 2192 } 2195 PGMPhysInvalidatePageMapTLB(pVM); 2196 2193 pgmPhysInvalidatePageMapTLB(pVM); 2194 2195 pgmUnlock(pVM); 2197 2196 return rc; 2198 2197 } … … 2214 2213 VM_ASSERT_EMT(pVM); 2215 2214 2216 /** @todo this needs to own the PGM lock! */ 2215 int rc = pgmLock(pVM); 2216 AssertRCReturn(rc, rc); 2217 2217 2218 /* 2218 2219 * First deregister the handler, then check if we should remove the ram range. 2219 2220 */ 2220 intrc = PGMHandlerPhysicalDeregister(pVM, GCPhys);2221 rc = PGMHandlerPhysicalDeregister(pVM, GCPhys); 2221 2222 if (RT_SUCCESS(rc)) 2222 2223 { … … 2291 2292 AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage)); 2292 2293 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO) 2293 PGM_PAGE_SET_TYPE(p Page, PGMPAGETYPE_RAM);2294 PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM); 2294 2295 } 2295 2296 break; … … 2308 2309 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); 2309 2310 2310 PGMPhysInvalidatePageMapTLB(pVM);2311 pgmPhysInvalidatePageMapTLB(pVM); 2311 2312 pgmPhysInvalidRamRangeTlbs(pVM); 2313 pgmUnlock(pVM); 2312 2314 return rc; 2313 2315 } … … 2459 2461 *ppv = pvPages; 2460 2462 RTMemTmpFree(paPages); 2461 PGMPhysInvalidatePageMapTLB(pVM);2463 pgmPhysInvalidatePageMapTLB(pVM); 2462 2464 return VINF_SUCCESS; 2463 2465 } … … 2571 2573 } 2572 2574 } 2573 PGMPhysInvalidatePageMapTLB(pVM);2575 pgmPhysInvalidatePageMapTLB(pVM); 2574 2576 pgmUnlock(pVM); 2575 2577 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc; … … 2681 2683 2682 2684 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc); 2683 PGM_PAGE_SET_HCPHYS(p PageDst, HCPhys);2684 PGM_PAGE_SET_TYPE(p PageDst, PGMPAGETYPE_MMIO2);2685 PGM_PAGE_SET_STATE(p PageDst, PGM_PAGE_STATE_ALLOCATED);2686 PGM_PAGE_SET_PDE_TYPE(p PageDst, PGM_PAGE_PDE_TYPE_DONTCARE);2687 PGM_PAGE_SET_PTE_INDEX(p PageDst, 0);2688 PGM_PAGE_SET_TRACKING(p PageDst, 0);2685 PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys); 2686 PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2); 2687 PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED); 2688 PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE); 2689 PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0); 2690 PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0); 2689 2691 2690 2692 pVM->pgm.s.cZeroPages--; … … 2695 2697 2696 2698 /* Flush physical page map TLB. */ 2697 PGMPhysInvalidatePageMapTLB(pVM);2699 pgmPhysInvalidatePageMapTLB(pVM); 2698 2700 2699 2701 if (cPendingPages) … … 2721 2723 while (cPagesLeft-- > 0) 2722 2724 { 2723 PGM_PAGE_SET_TRACKING(p PageSrc, 0);2724 PGM_PAGE_SET_PTE_INDEX(p PageSrc, 0);2725 PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0); 2726 PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0); 2725 2727 pPageSrc++; 2726 2728 } … … 2733 2735 } 2734 2736 2735 PGMPhysInvalidatePageMapTLB(pVM);2737 pgmPhysInvalidatePageMapTLB(pVM); 2736 2738 return VINF_SUCCESS; 2737 2739 } … … 2791 2793 2792 2794 /* Flush physical page map TLB. */ 2793 PGMPhysInvalidatePageMapTLB(pVM);2795 pgmPhysInvalidatePageMapTLB(pVM); 2794 2796 2795 2797 GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */ … … 2817 2819 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); 2818 2820 2819 PGMPhysInvalidatePageMapTLB(pVM);2821 pgmPhysInvalidatePageMapTLB(pVM); 2820 2822 pgmPhysInvalidRamRangeTlbs(pVM); 2821 2823 pgmUnlock(pVM); … … 2939 2941 2940 2942 /** 2941 * Registers a ROM image. 2942 * 2943 * Shadowed ROM images requires double the amount of backing memory, so, 2944 * don't use that unless you have to. Shadowing of ROM images is process 2945 * where we can select where the reads go and where the writes go. On real 2946 * hardware the chipset provides means to configure this. We provide 2947 * PGMR3PhysProtectROM() for this purpose. 2948 * 2949 * A read-only copy of the ROM image will always be kept around while we 2950 * will allocate RAM pages for the changes on demand (unless all memory 2951 * is configured to be preallocated). 2943 * Worker for PGMR3PhysRomRegister. 2944 * 2945 * This is here to simplify lock management, i.e. the caller does all the 2946 * locking and we can simply return without needing to remember to unlock 2947 * anything first. 2952 2948 * 2953 2949 * @returns VBox status. … … 2964 2960 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY. 2965 2961 * @param pszDesc Pointer to description string. This must not be freed. 2966 * 2967 * @remark There is no way to remove the rom, automatically on device cleanup or 2968 * manually from the device yet. This isn't difficult in any way, it's 2969 * just not something we expect to be necessary for a while. 2970 */ 2971 VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb, 2972 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc) 2973 { 2974 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n", 2975 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc)); 2976 2962 */ 2963 static int pgmR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb, 2964 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc) 2965 { 2977 2966 /* 2978 2967 * Validate input. … … 3082 3071 } 3083 3072 3084 pgmLock(pVM);3085 3073 rc = GMMR3AllocatePagesPerform(pVM, pReq); 3086 pgmUnlock(pVM);3087 3074 if (RT_FAILURE(rc)) 3088 3075 { … … 3103 3090 if (RT_SUCCESS(rc)) 3104 3091 { 3105 pgmLock(pVM);3106 3107 3092 /* 3108 3093 * Initialize and insert the RAM range (if required). … … 3141 3126 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++) 3142 3127 { 3143 PGM_PAGE_SET_TYPE(p Page, PGMPAGETYPE_ROM);3144 PGM_PAGE_SET_HCPHYS(p Page, pReq->aPages[iPage].HCPhysGCPhys);3145 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ALLOCATED);3146 PGM_PAGE_SET_PAGEID(p Page, pReq->aPages[iPage].idPage);3147 PGM_PAGE_SET_PDE_TYPE(p Page, PGM_PAGE_PDE_TYPE_DONTCARE);3148 PGM_PAGE_SET_PTE_INDEX(p Page, 0);3149 PGM_PAGE_SET_TRACKING(p Page, 0);3128 PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_ROM); 3129 PGM_PAGE_SET_HCPHYS(pVM, pPage, pReq->aPages[iPage].HCPhysGCPhys); 3130 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED); 3131 PGM_PAGE_SET_PAGEID(pVM, pPage, pReq->aPages[iPage].idPage); 3132 PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE); 3133 PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0); 3134 PGM_PAGE_SET_TRACKING(pVM, pPage, 0); 3150 3135 3151 3136 pRomPage->Virgin = *pPage; … … 3159 3144 3160 3145 /* Flush physical page map TLB. */ 3161 PGMPhysInvalidatePageMapTLB(pVM); 3162 3163 pgmUnlock(pVM); 3146 pgmPhysInvalidatePageMapTLB(pVM); 3164 3147 3165 3148 … … 3199 3182 if (RT_SUCCESS(rc)) 3200 3183 { 3201 pgmLock(pVM);3202 3203 3184 /* 3204 3185 * Copy the image over to the virgin pages. … … 3285 3266 } 3286 3267 3287 PGMPhysInvalidatePageMapTLB(pVM);3268 pgmPhysInvalidatePageMapTLB(pVM); 3288 3269 GMMR3AllocatePagesCleanup(pReq); 3289 pgmUnlock(pVM);3290 3270 return VINF_SUCCESS; 3291 3271 } … … 3293 3273 /* bail out */ 3294 3274 3295 pgmUnlock(pVM);3296 3275 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys); 3297 3276 AssertRC(rc2); 3298 pgmLock(pVM);3299 3277 } 3300 3278 … … 3311 3289 GMMR3FreeAllocatedPages(pVM, pReq); 3312 3290 GMMR3AllocatePagesCleanup(pReq); 3291 return rc; 3292 } 3293 3294 3295 /** 3296 * Registers a ROM image. 3297 * 3298 * Shadowed ROM images requires double the amount of backing memory, so, 3299 * don't use that unless you have to. Shadowing of ROM images is process 3300 * where we can select where the reads go and where the writes go. On real 3301 * hardware the chipset provides means to configure this. We provide 3302 * PGMR3PhysProtectROM() for this purpose. 3303 * 3304 * A read-only copy of the ROM image will always be kept around while we 3305 * will allocate RAM pages for the changes on demand (unless all memory 3306 * is configured to be preallocated). 3307 * 3308 * @returns VBox status. 3309 * @param pVM VM Handle. 3310 * @param pDevIns The device instance owning the ROM. 3311 * @param GCPhys First physical address in the range. 3312 * Must be page aligned! 3313 * @param cb The size of the range (in bytes). 3314 * Must be page aligned! 3315 * @param pvBinary Pointer to the binary data backing the ROM image. 3316 * @param cbBinary The size of the binary data pvBinary points to. 3317 * This must be less or equal to @a cb. 3318 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED 3319 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY. 3320 * @param pszDesc Pointer to description string. This must not be freed. 3321 * 3322 * @remark There is no way to remove the rom, automatically on device cleanup or 3323 * manually from the device yet. This isn't difficult in any way, it's 3324 * just not something we expect to be necessary for a while. 3325 */ 3326 VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb, 3327 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc) 3328 { 3329 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n", 3330 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc)); 3331 pgmLock(pVM); 3332 int rc = pgmR3PhysRomRegister(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc); 3313 3333 pgmUnlock(pVM); 3314 3334 return rc; … … 3428 3448 int pgmR3PhysRomReset(PVM pVM) 3429 3449 { 3430 Assert(PGMIsLockOwner(pVM));3450 PGM_LOCK_ASSERT_OWNER(pVM); 3431 3451 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3) 3432 3452 { … … 3671 3691 static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser) 3672 3692 { 3673 Assert(PGMIsLockOwner((PVM)pvUser)); 3693 PGM_LOCK_ASSERT_OWNER(pVM); 3694 3674 3695 /* Age compression - ASSUMES iNow == 4. */ 3675 3696 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode; … … 3785 3806 static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM) 3786 3807 { 3787 Assert(PGMIsLockOwner(pVM));3808 PGM_LOCK_ASSERT_OWNER(pVM); 3788 3809 3789 3810 /* … … 3935 3956 int rc; 3936 3957 3937 Assert(PGMIsLockOwner(pVM)); 3958 PGM_LOCK_ASSERT_OWNER(pVM); 3959 3938 3960 /* 3939 3961 * Allocate a new tracking structure first. … … 4037 4059 } 4038 4060 /* The page map TLB references chunks, so invalidate that one too. */ 4039 PGMPhysInvalidatePageMapTLB(pVM);4061 pgmPhysInvalidatePageMapTLB(pVM); 4040 4062 pgmUnlock(pVM); 4041 4063 } … … 4106 4128 */ 4107 4129 pVM->pgm.s.cPrivatePages++; 4108 PGM_PAGE_SET_HCPHYS(p Page, HCPhys);4109 PGM_PAGE_SET_PAGEID(p Page, idPage);4110 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ALLOCATED);4111 PGM_PAGE_SET_PDE_TYPE(p Page, PGM_PAGE_PDE_TYPE_PDE);4112 PGM_PAGE_SET_PTE_INDEX(p Page, 0);4113 PGM_PAGE_SET_TRACKING(p Page, 0);4130 PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys); 4131 PGM_PAGE_SET_PAGEID(pVM, pPage, idPage); 4132 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED); 4133 PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE); 4134 PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0); 4135 PGM_PAGE_SET_TRACKING(pVM, pPage, 0); 4114 4136 4115 4137 /* Somewhat dirty assumption that page ids are increasing. */ … … 4127 4149 /* Flush all TLBs. */ 4128 4150 PGM_INVL_ALL_VCPU_TLBS(pVM); 4129 PGMPhysInvalidatePageMapTLB(pVM);4151 pgmPhysInvalidatePageMapTLB(pVM); 4130 4152 } 4131 4153 pVM->pgm.s.cLargeHandyPages = 0; … … 4323 4345 * Assert sanity. 4324 4346 */ 4325 Assert(PGMIsLockOwner(pVM));4347 PGM_LOCK_ASSERT_OWNER(pVM); 4326 4348 if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM 4327 4349 && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW)) … … 4359 4381 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED) 4360 4382 { 4361 PGM_PAGE_SET_WRITTEN_TO(p Page);4383 PGM_PAGE_SET_WRITTEN_TO(pVM, pPage); 4362 4384 pVM->pgm.s.cWrittenToPages++; 4363 4385 } … … 4366 4388 * pPage = ZERO page. 4367 4389 */ 4368 PGM_PAGE_SET_HCPHYS(p Page, pVM->pgm.s.HCPhysZeroPg);4369 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ZERO);4370 PGM_PAGE_SET_PAGEID(p Page, NIL_GMM_PAGEID);4371 PGM_PAGE_SET_PDE_TYPE(p Page, PGM_PAGE_PDE_TYPE_DONTCARE);4372 PGM_PAGE_SET_PTE_INDEX(p Page, 0);4373 PGM_PAGE_SET_TRACKING(p Page, 0);4390 PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg); 4391 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO); 4392 PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID); 4393 PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE); 4394 PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0); 4395 PGM_PAGE_SET_TRACKING(pVM, pPage, 0); 4374 4396 4375 4397 /* Flush physical page map TLB entry. */ 4376 PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);4398 pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys); 4377 4399 4378 4400 /* -
trunk/src/VBox/VMM/VMMR3/PGMPool.cpp
r36960 r37354 809 809 iPage = pRam->cb >> PAGE_SHIFT; 810 810 while (iPage-- > 0) 811 PGM_PAGE_SET_TRACKING( &pRam->aPages[iPage], 0);811 PGM_PAGE_SET_TRACKING(pVM, &pRam->aPages[iPage], 0); 812 812 } 813 813 … … 906 906 void pgmR3PoolWriteProtectPages(PVM pVM) 907 907 { 908 Assert(PGMIsLockOwner(pVM));908 PGM_LOCK_ASSERT_OWNER(pVM); 909 909 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); 910 910 unsigned cLeft = pPool->cUsedPages; -
trunk/src/VBox/VMM/VMMR3/PGMSavedState.cpp
r37110 r37354 282 282 static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM) 283 283 { 284 Assert(PGMIsLockOwner(pVM));284 PGM_LOCK_ASSERT_OWNER(pVM); 285 285 286 286 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3) … … 673 673 static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM) 674 674 { 675 Assert(PGMIsLockOwner(pVM));675 PGM_LOCK_ASSERT_OWNER(pVM); 676 676 677 677 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3) … … 1344 1344 { 1345 1345 Assert(paLSPages[iPage].fWriteMonitored); 1346 PGM_PAGE_CLEAR_WRITTEN_TO( &pCur->aPages[iPage]);1346 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]); 1347 1347 Assert(pVM->pgm.s.cWrittenToPages > 0); 1348 1348 pVM->pgm.s.cWrittenToPages--; … … 1472 1472 { 1473 1473 AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */ 1474 PGM_PAGE_SET_STATE( &pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);1474 PGM_PAGE_SET_STATE(pVM, &pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED); 1475 1475 Assert(pVM->pgm.s.cMonitoredPages > 0); 1476 1476 pVM->pgm.s.cMonitoredPages--; … … 1478 1478 if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage])) 1479 1479 { 1480 PGM_PAGE_CLEAR_WRITTEN_TO( &pCur->aPages[iPage]);1480 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]); 1481 1481 Assert(pVM->pgm.s.cWrittenToPages > 0); 1482 1482 pVM->pgm.s.cWrittenToPages--; … … 1639 1639 } 1640 1640 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE); 1641 PGM_PAGE_CLEAR_WRITTEN_TO(p CurPage);1641 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pCurPage); 1642 1642 PGM_PAGE_CLEAR_FT_DIRTY(pCurPage); 1643 1643 } … … 1768 1768 { 1769 1769 PPGMPAGE pPage = &pCur->aPages[iPage]; 1770 PGM_PAGE_CLEAR_WRITTEN_TO(p Page);1770 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage); 1771 1771 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED) 1772 1772 { 1773 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ALLOCATED);1773 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED); 1774 1774 cMonitoredPages++; 1775 1775 } … … 2667 2667 if (uVersion == PGM_SAVED_STATE_VERSION_BALLOON_BROKEN) 2668 2668 break; 2669 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_ZERO);2669 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO); 2670 2670 break; 2671 2671 } … … 2714 2714 } 2715 2715 Assert(PGM_PAGE_IS_ZERO(pPage)); 2716 PGM_PAGE_SET_STATE(p Page, PGM_PAGE_STATE_BALLOONED);2716 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED); 2717 2717 break; 2718 2718 }
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