Changeset 37501 in vbox
- Timestamp:
- Jun 16, 2011 3:08:48 PM (14 years ago)
- svn:sync-xref-src-repo-rev:
- 72326
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/PC/DevHPET.cpp
r37500 r37501 195 195 PCPDMHPETHLPRC pHpetHlpRC; 196 196 197 /* Timer structures. */197 /** Timer structures. */ 198 198 HpetTimer aTimers[HPET_NUM_TIMERS]; 199 199 200 /* Offset realtive to the systemclock. */200 /** Offset realtive to the virtual sync clock. */ 201 201 uint64_t u64HpetOffset; 202 202 203 /* Memory-mapped, software visible registers */ 204 /* capabilities. */ 203 /** @name Memory-mapped, software visible registers 204 * @{ */ 205 /** Capabilities. */ 205 206 uint64_t u64Capabilities; 206 /* Configuration. */207 /** Configuration. */ 207 208 uint64_t u64HpetConfig; 208 /* Interrupt status register. */209 /** Interrupt status register. */ 209 210 uint64_t u64Isr; 210 /* Main counter. */211 /** Main counter. */ 211 212 uint64_t u64HpetCounter; 212 213 /* Global device lock. */ 213 /** @} */ 214 215 /** Global device lock. */ 214 216 PDMCRITSECT csLock; 215 217 216 /* If we emulate ICH9 HPET (different frequency). */ 218 /** If we emulate ICH9 HPET (different frequency). 219 * @todo different number of timers */ 217 220 uint8_t fIch9; 218 221 uint8_t padding0[7]; … … 1083 1086 { 1084 1087 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *); 1085 unsigned i;1086 1088 LogFlow(("hpetRelocate:\n")); 1087 1089 … … 1089 1091 pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns); 1090 1092 1091 for ( i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)1093 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++) 1092 1094 { 1093 1095 HpetTimer *pTm = &pThis->aTimers[i]; … … 1107 1109 { 1108 1110 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *); 1109 unsigned i;1110 1111 1111 LogFlow(("hpetReset:\n")); 1112 1112 1113 1113 pThis->u64HpetConfig = 0; 1114 for ( i = 0; i < HPET_NUM_TIMERS; i++)1114 for (unsigned i = 0; i < HPET_NUM_TIMERS; i++) 1115 1115 { 1116 1116 HpetTimer *pHpetTimer = &pThis->aTimers[i]; 1117 pHpetTimer->idxTimer = i; 1117 Assert(pHpetTimer->idxTimer == i); 1118 1118 1119 /* capable of periodic operations and 64-bits */ 1119 1120 if (pThis->fIch9) … … 1136 1137 uint32_t u32Vendor = 0x8086; 1137 1138 /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */ 1138 uint32_t u32Caps = 1139 (1 << 15) /* LEG_RT_CAP, LegacyReplacementRoute capable */ | 1140 (1 << 13) /* COUNTER_SIZE_CAP, main counter is 64-bit capable */ | 1141 /* Actually ICH9 has 4 timers, but to avoid breaking saved state we'll stick with 3 so far. */ 1142 (HPET_NUM_TIMERS << 8) /* NUM_TIM_CAP, number of timers -1 */ | 1143 1 /* REV_ID, revision, must not be 0 */; 1139 uint32_t u32Caps = (1 << 15) /* LEG_RT_CAP - LegacyReplacementRoute capable. */ 1140 | (1 << 13) /* COUNTER_SIZE_CAP - Main counter is 64-bit capable. */ 1141 | (HPET_NUM_TIMERS << 8) /* NUM_TIM_CAP - Number of timers -1. 1142 Actually ICH9 has 4 timers, but to avoid breaking 1143 saved state we'll stick with 3 so far. */ /** @todo fix this ICH9 timer count bug. */ 1144 | 1 /* REV_ID - Revision, must not be 0 */ 1145 ; 1144 1146 pThis->u64Capabilities = (u32Vendor << 16) | u32Caps; 1145 1147 pThis->u64Capabilities |= ((uint64_t)(pThis->fIch9 ? HPET_CLK_PERIOD_ICH9 : HPET_CLK_PERIOD) << 32); … … 1147 1149 /* Notify PIT/RTC devices */ 1148 1150 hpetLegacyMode(pThis, false); 1149 }1150 1151 /**1152 * Initialization routine.1153 *1154 * @returns VBox status.1155 * @param pDevIns The device instance data.1156 */1157 static int hpetInit(PPDMDEVINS pDevIns)1158 {1159 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);1160 1161 pThis->pDevInsR3 = pDevIns;1162 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);1163 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);1164 1165 for (unsigned i = 0; i < HPET_NUM_TIMERS; i++)1166 {1167 HpetTimer *pHpetTimer = &pThis->aTimers[i];1168 1169 pHpetTimer->pHpetR3 = pThis;1170 pHpetTimer->pHpetR0 = PDMINS_2_DATA_R0PTR(pDevIns);1171 pHpetTimer->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);1172 1173 int rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hpetTimer, pHpetTimer,1174 TMTIMER_FLAGS_NO_CRIT_SECT, "HPET Timer",1175 &pThis->aTimers[i].pTimerR3);1176 if (RT_FAILURE(rc))1177 return rc;1178 pThis->aTimers[i].pTimerRC = TMTimerRCPtr(pThis->aTimers[i].pTimerR3);1179 pThis->aTimers[i].pTimerR0 = TMTimerR0Ptr(pThis->aTimers[i].pTimerR3);1180 /// @todo TMR3TimerSetCritSect(pThis->aTimers[i].pTimerR3, &pThis->csLock);1181 }1182 1183 hpetReset(pDevIns);1184 1185 return VINF_SUCCESS;1186 1151 } 1187 1152 … … 1257 1222 N_("Configuration error: failed to read ICH9 as boolean")); 1258 1223 1259 /* Initialize the device state */ 1260 pThis->fIch9 = (uint8_t)fIch9; 1261 1262 rc = hpetInit(pDevIns); 1263 if (RT_FAILURE(rc)) 1264 return rc; 1265 1224 /* 1225 * Initialize the device state 1226 */ 1266 1227 pThis->pDevInsR3 = pDevIns; 1267 1228 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 1268 1229 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 1230 pThis->fIch9 = (uint8_t)fIch9; 1231 1232 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csLock, RT_SRC_POS, "HPET#%u", pDevIns->iInstance); 1233 AssertRCReturn(rc, rc); 1234 1235 /* Init timers. */ 1236 for (unsigned i = 0; i < HPET_NUM_TIMERS; i++) 1237 { 1238 HpetTimer *pHpetTimer = &pThis->aTimers[i]; 1239 1240 pHpetTimer->idxTimer = i; 1241 pHpetTimer->pHpetR3 = pThis; 1242 pHpetTimer->pHpetR0 = PDMINS_2_DATA_R0PTR(pDevIns); 1243 pHpetTimer->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns); 1244 1245 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hpetTimer, pHpetTimer, 1246 TMTIMER_FLAGS_NO_CRIT_SECT, "HPET Timer", 1247 &pThis->aTimers[i].pTimerR3); 1248 AssertRCReturn(rc, rc); 1249 pThis->aTimers[i].pTimerRC = TMTimerRCPtr(pThis->aTimers[i].pTimerR3); 1250 pThis->aTimers[i].pTimerR0 = TMTimerR0Ptr(pThis->aTimers[i].pTimerR3); 1251 /// @todo TMR3TimerSetCritSect(pThis->aTimers[i].pTimerR3, &pThis->csLock); 1252 } 1253 1254 hpetReset(pDevIns); 1269 1255 1270 1256 /* … … 1277 1263 1278 1264 /* 1279 * Initialize critical section.1280 */1281 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csLock, RT_SRC_POS, "HPET#%u", pDevIns->iInstance);1282 if (RT_FAILURE(rc))1283 return PDMDEV_SET_ERROR(pDevIns, rc, N_("HPET cannot initialize critical section"));1284 1285 /*1286 1265 * Register the MMIO range, PDM API requests page aligned 1287 1266 * addresses and sizes. … … 1289 1268 rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, 0x1000, pThis, 1290 1269 hpetMMIOWrite, hpetMMIORead, NULL, "HPET Memory"); 1291 if (RT_FAILURE(rc)) 1292 { 1293 AssertMsgRC(rc, ("Cannot register MMIO: %Rrc\n", rc)); 1294 return rc; 1295 } 1270 AssertRCReturn(rc, rc); 1296 1271 1297 1272 if (fRCEnabled) … … 1299 1274 rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, 0x1000, 0, 1300 1275 "hpetMMIOWrite", "hpetMMIORead", NULL); 1301 if (RT_FAILURE(rc)) 1302 return rc; 1276 AssertRCReturn(rc, rc); 1303 1277 1304 1278 pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns); 1305 if (!pThis->pHpetHlpRC) 1306 { 1307 AssertReleaseMsgFailed(("cannot get RC helper\n")); 1308 return VERR_INTERNAL_ERROR; 1309 } 1279 AssertReturn(pThis->pHpetHlpRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR); 1310 1280 } 1311 1281 … … 1314 1284 rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, 0x1000, 0, 1315 1285 "hpetMMIOWrite", "hpetMMIORead", NULL); 1316 if (RT_FAILURE(rc)) 1317 return rc; 1286 AssertRCReturn(rc, rc); 1318 1287 1319 1288 pThis->pHpetHlpR0 = pThis->pHpetHlpR3->pfnGetR0Helpers(pDevIns); 1320 if (!pThis->pHpetHlpR0) 1321 { 1322 AssertReleaseMsgFailed(("cannot get R0 helper\n")); 1323 return VERR_INTERNAL_ERROR; 1324 } 1289 AssertReturn(pThis->pHpetHlpR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR); 1325 1290 } 1326 1291 1327 1292 /* Register SSM callbacks */ 1328 1293 rc = PDMDevHlpSSMRegister3(pDevIns, HPET_SAVED_STATE_VERSION, sizeof(*pThis), hpetLiveExec, hpetSaveExec, hpetLoadExec); 1329 if (RT_FAILURE(rc)) 1330 return rc; 1294 AssertRCReturn(rc, rc); 1331 1295 1332 1296 /**
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