Changeset 39034 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Oct 19, 2011 11:43:52 AM (13 years ago)

Author:

vboxsync

Message:

VMM,INTNET: Addressing unused variable warnings.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• EMAll.cpp (modified) (2 diffs)
• IEMAllCImpl.cpp.h (modified) (2 diffs)
• IOMAllMMIO.cpp (modified) (1 diff)
• PGMAll.cpp (modified) (8 diffs)
• PGMAllBth.h (modified) (11 diffs)
• PGMAllPhys.cpp (modified) (2 diffs)
• PGMAllPool.cpp (modified) (3 diffs)
• TMAll.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -118 +118 @@
     PDISCPUSTATE  pDis   = (PDISCPUSTATE)pvUserdata;
     PEMDISSTATE   pState = (PEMDISSTATE)pDis->apvUserData[0];
+# ifndef IN_RING0
     PVM           pVM    = pState->pVM;
+# endif
     PVMCPU        pVCpu  = pState->pVCpu;
 
@@ -3113 +3115 @@
     Assert(!IOMIsLockOwner(pVM));
     int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
-    AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
+    AssertRCSuccess(rc);
 }
 

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -1510 +1510 @@
 IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
 {
-    PCPUMCTX        pCtx = pIemCpu->CTX_SUFF(pCtx);
+    /*PCPUMCTX        pCtx = pIemCpu->CTX_SUFF(pCtx);*/
     uint16_t       *pSel = iemSRegRef(pIemCpu, iSegReg);
     PCPUMSELREGHID  pHid = iemSRegGetHid(pIemCpu, iSegReg);
@@ -1799 +1799 @@
                 IEMMODE,  enmEffOpSize)
 {
-    PCPUMCTX        pCtx = pIemCpu->CTX_SUFF(pCtx);
+    /*PCPUMCTX        pCtx = pIemCpu->CTX_SUFF(pCtx);*/
     VBOXSTRICTRC    rcStrict;
 

trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp

@@ -1353 +1353 @@
 VMMDECL(VBOXSTRICTRC) IOMMMIOPhysHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault)
 {
-    int rc2 = IOM_LOCK(pVM);
+    int rc2 = IOM_LOCK(pVM); NOREF(rc2);
 #ifndef IN_RING3
     if (rc2 == VERR_SEM_BUSY)

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -1057 +1057 @@
 static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
 {
-    PPGMCPU        pPGM          = &pVCpu->pgm.s;
     PVM            pVM           = pVCpu->CTX_SUFF(pVM);
     PPGMPOOL       pPool         = pVM->pgm.s.CTX_SUFF(pPool);
@@ -1156 +1155 @@
 DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
 {
-    PPGMCPU         pPGM = &pVCpu->pgm.s;
     const unsigned  iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     PCX86PML4E      pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
 
-    PGM_LOCK_ASSERT_OWNER(PGMCPU2VM(pPGM));
+    PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
 
     AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
@@ -1922 +1920 @@
 VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
 {
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
-
     VMCPU_ASSERT_EMT(pVCpu);
     LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
 
     /* We assume we're only called in nested paging mode. */
-    Assert(pVM->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
-    Assert(pVM->pgm.s.fMappingsDisabled);
+    Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
+    Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsDisabled);
     Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
 
@@ -1977 +1973 @@
 VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
 {
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
     int rc;
 
@@ -2021 +2016 @@
         pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
 
-        RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
+        RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
         RTGCPHYS GCPhysCR3;
         switch (pVCpu->pgm.s.enmGuestMode)
@@ -2089 +2084 @@
         {
             pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
-            Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
+            Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
+            Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsDisabled);
         }
     }
@@ -2119 +2115 @@
 VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
 {
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
     PGMMODE enmGuestMode;
 
@@ -2164 +2159 @@
 
 #ifdef IN_RING3
-    return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
+    return PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
 #else
     LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -442 +442 @@
 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
 {
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
 
     *pfLockTaken = false;
@@ -1162 +1162 @@
 # else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
     /* PML4 */
-    const unsigned  iPml4     = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
+    /*const unsigned  iPml4     = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;*/
     const unsigned  iPdpt     = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     const unsigned  iPDDst    = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
@@ -1802 +1802 @@
 static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
 {
-    PVM      pVM = pVCpu->CTX_SUFF(pVM);
-    PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
+    PVM      pVM   = pVCpu->CTX_SUFF(pVM);
+    PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
     LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
 
@@ -1951 +1951 @@
                          */
                         unsigned        iPTDst      = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
-                        const unsigned  iPTDstPage  = iPTDst;
 #  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
                         /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
@@ -2538 +2537 @@
 {
     PVM             pVM      = pVCpu->CTX_SUFF(pVM);
-    PPGMPOOL        pPool    = pVM->pgm.s.CTX_SUFF(pPool);
+    PPGMPOOL        pPool    = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
 
 #if 0 /* rarely useful; leave for debugging. */
@@ -2627 +2626 @@
         rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
 #   else
-        AssertFailed();     /* can't happen for amd64 */
+        AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
 #   endif
         if (RT_FAILURE(rc))
@@ -3364 +3363 @@
 PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
 {
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
 
     LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
@@ -3553 +3552 @@
 PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
 {
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
 
     LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
@@ -3648 +3647 @@
     unsigned cErrors = 0;
     PVM      pVM     = pVCpu->CTX_SUFF(pVM);
-    PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
+    PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
 
 #if PGM_GST_TYPE == PGM_TYPE_PAE
@@ -4402 +4401 @@
 PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
 {
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
 
     /* Update guest paging info. */
@@ -4631 +4630 @@
 
     int rc  = VINF_SUCCESS;
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
 
     /*

trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp

@@ -1934 +1934 @@
 }
 
+#if 0 /*defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)*/
+
+/**
+ * Maps and locks a guest CR3 or PD (PAE) page.
+ *
+ * @returns VINF_SUCCESS on success.
+ * @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
+ *          page but has no physical backing.
+ * @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
+ *          GC physical address.
+ * @returns VERR_PGM_GCPHYS_RANGE_CROSSES_BOUNDARY if the range crosses
+ *          a dynamic ram chunk boundary
+ *
+ * @param   pVM         The VM handle.
+ * @param   GCPhys      The GC physical address to convert.
+ * @param   pR3Ptr      Where to store the R3 pointer on success.  This may or
+ *                      may not be valid in ring-0 depending on the
+ *                      VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 build option.
+ *
+ * @remarks The caller must own the PGM lock.
+ */
+int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr)
+{
+
+    PPGMRAMRANGE pRam;
+    PPGMPAGE pPage;
+    int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
+    if (RT_SUCCESS(rc))
+        rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)pR3Ptr);
+    Assert(rc <= VINF_SUCCESS);
+    return rc;
+}
+
+
+int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr)
+{
+
+}
+
+#endif
 
 /**
@@ -2048 +2088 @@
      * Deal with any physical handlers.
      */
+#ifdef IN_RING3
     PPGMPHYSHANDLER pPhys = NULL;
+#endif
     if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL)
     {

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -2163 +2163 @@
 static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
 {
-#ifndef IN_RC
-    const PVM pVM = pPool->CTX_SUFF(pVM);
-#endif
     /*
      * Look up the GCPhys in the hash.
@@ -5095 +5092 @@
 PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
 {
-    PVM pVM = pPool->CTX_SUFF(pVM);
-    PGM_LOCK_ASSERT_OWNER(pVM);
+    PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
 
     /*
@@ -5117 +5113 @@
 PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys)
 {
-    PVM pVM = pPool->CTX_SUFF(pVM);
-    PGM_LOCK_ASSERT_OWNER(pVM);
+    PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
     return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
 }

trunk/src/VBox/VMM/VMMAll/TMAll.cpp

@@ -2103 +2103 @@
 VMMDECL(int) TMTimerSetMillies(PTMTIMER pTimer, uint32_t cMilliesToNext)
 {
-    PVM    pVM   = pTimer->CTX_SUFF(pVM);
-    PVMCPU pVCpu = &pVM->aCpus[0];  /* just take the first VCPU */
-
     switch (pTimer->enmClock)
     {
@@ -2136 +2133 @@
 VMMDECL(int) TMTimerSetMicro(PTMTIMER pTimer, uint64_t cMicrosToNext)
 {
-    PVM    pVM   = pTimer->CTX_SUFF(pVM);
-    PVMCPU pVCpu = &pVM->aCpus[0];  /* just take the first VCPU */
-
     switch (pTimer->enmClock)
     {
@@ -2169 +2163 @@
 VMMDECL(int) TMTimerSetNano(PTMTIMER pTimer, uint64_t cNanosToNext)
 {
-    PVM    pVM   = pTimer->CTX_SUFF(pVM);
-    PVMCPU pVCpu = &pVM->aCpus[0];  /* just take the first VCPU */
-
     switch (pTimer->enmClock)
     {