VirtualBox

Changeset 39053 in vbox for trunk/src/VBox/Devices/PC


Ignore:
Timestamp:
Oct 20, 2011 1:37:40 PM (13 years ago)
Author:
vboxsync
Message:

DevApic.cpp: Don't assert on invalid register accesses, do a DBGFStop instead.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/PC/DevAPIC.cpp

    r37636 r39053  
    324324                        uint8_t delivery_mode, uint8_t vector_num,
    325325                        uint8_t polarity, uint8_t trigger_mode);
    326 static int apic_get_arb_pri(APICState *s);
    327 static int apic_get_ppr(APICState *s);
    328 static uint32_t apic_get_current_count(APICDeviceInfo* pDev, APICState *s);
     326static int apic_get_arb_pri(APICState const *s);
     327static int apic_get_ppr(APICState const *s);
     328static uint32_t apic_get_current_count(APICDeviceInfo const *pDev, APICState const *s);
    329329static void apicTimerSetInitialCount(APICDeviceInfo *pDev, APICState *s, uint32_t initial_count);
    330330static void apicTimerSetLvt(APICDeviceInfo *pDev, APICState *pApic, uint32_t fNew);
    … …  
    694694            /* else: fall thru */
    695695        default:
    696             AssertMsgFailed(("unknown iReg %x\n", iReg));
     696            Log(("apicWriteRegister/%u: unknown index %#x\n", pApic->phys_id, iReg));
     697            rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
     698                                   "unknown index %#x (id=%u)\n", iReg, pApic->phys_id);
    697699            pApic->esr |= ESR_ILLEGAL_ADDRESS;
    698700            break;
    … …  
    803805             */
    804806        default:
    805             AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
    806807            /**
    807808             * @todo: according to spec when APIC writes to ESR it msut raise error interrupt,
    808809             *        i.e. LVT[5]
    809810             */
     811            Log(("apicReadMSR/%u: unknown index %#x\n", apic->phys_id, index));
     812            rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
     813                                   "unknown index %#x (id=%u)\n", index, apic->phys_id);
    810814            apic->esr |= ESR_ILLEGAL_ADDRESS;
    811815            val = 0;
    … …  
    923927
    924928/* return -1 if no bit is set */
    925 static int get_highest_priority_int(uint32_t *tab)
     929static int get_highest_priority_int(uint32_t const *tab)
    926930{
    927931    int i;
    … …  
    934938}
    935939
    936 static int apic_get_ppr(APICState *s)
     940static int apic_get_ppr(APICState const *s)
    937941{
    938942    int tpr, isrv, ppr;
    … …  
    960964}
    961965
    962 static int apic_get_arb_pri(APICState *s)
     966static int apic_get_arb_pri(APICState const *s)
    963967{
    964968    /* XXX: arbitration */
    … …  
    12321236 * May return to ring-3 to acquire the TM and PDM lock.
    12331237 */
    1234 static uint32_t apic_get_current_count(APICDeviceInfo *pDev, APICState *s)
     1238static uint32_t apic_get_current_count(APICDeviceInfo const *pDev, APICState const *s)
    12351239{
    12361240    int64_t d;
    … …  
    14761480# endif /* IN_RING3 */
    14771481
    1478 static uint32_t apic_mem_readl(APICDeviceInfo* pDev, APICState *s, RTGCPHYS addr)
    1479 {
    1480     uint32_t val;
    1481     int index;
    1482 
    1483     index = (addr >> 4) & 0xff;
    1484 
    1485     switch(index) {
     1482static int apic_mem_readl(APICDeviceInfo *pDev, APICState *s, RTGCPHYS addr, uint32_t *pu32)
     1483{
     1484    int         rc = VINF_SUCCESS;
     1485    int         index = (addr >> 4) & 0xff;
     1486    uint32_t    val;
     1487
     1488    switch (index) {
    14861489    case 0x02: /* id */
    14871490        val = s->id << 24;
    … …  
    15431546        break;
    15441547    case 0x2f:
    1545         /**
    1546          * Correctable machine check exception vector, @todo: implement me!
     1548        /** @todo
     1549         * Correctable machine check exception vector, implement me!
    15471550         */
    15481551    default:
    1549         AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
    15501552        s->esr |= ESR_ILLEGAL_ADDRESS;
    1551         val = 0;
    1552         break;
     1553        *pu32 = 0;
     1554        Log(("APIC/%u: unknown index %#x (%RGp)\n", s->phys_id, index, addr));
     1555        return PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
     1556                                 "unknown index %#x (%RGp) (id=%u)\n", index, addr, s->phys_id);
    15531557    }
    15541558#ifdef DEBUG_APIC
    15551559    Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
    15561560#endif
    1557     return val;
     1561    *pu32 = val;
     1562    return rc;
    15581563}
    15591564
    … …  
    16451650
    16461651    int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
     1652    AssertRCReturn(rc, rc);
    16471653    s->uHintedCountShift = s->uHintedInitialCount = 0;
    16481654    s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
    … …  
    16631669    Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id,  (uint64_t)GCPhysAddr));
    16641670
    1665     /** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
    1666                different physical addresses, see #3092) */
     1671    /** @todo add LAPIC range validity checks (different LAPICs can
     1672     *        theoretically have different physical addresses, see #3092) */
    16671673
    16681674    STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIORead));
    … …  
    16701676    {
    16711677        case 1:
     1678            /** @todo this is not how recent APIC behave!  We will fix
     1679             *        this via the IOM. */
    16721680            *(uint8_t *)pv = 0;
    16731681            break;
    16741682
    16751683        case 2:
     1684            /** @todo this is not how recent APIC behave! */
    16761685            *(uint16_t *)pv = 0;
    16771686            break;
    … …  
    16971706#endif /* experimental */
    16981707            APIC_LOCK(pDev, VINF_IOM_HC_MMIO_READ);
    1699             *(uint32_t *)pv = apic_mem_readl(pDev, s, GCPhysAddr);
     1708            int rc = apic_mem_readl(pDev, s, GCPhysAddr, (uint32_t *)pv);
    17001709            APIC_UNLOCK(pDev);
    1701             break;
     1710            return rc;
    17021711        }
    17031712        default:
    … …  
    17411750
    17421751/* Print a 8-dword LAPIC bit map (256 bits). */
    1743 static void lapicDumpVec(APICDeviceInfo  *pDev, APICState *lapic, PCDBGFINFOHLP pHlp, unsigned start)
    1744 {
    1745     unsigned    i;
    1746     uint32_t    val;
    1747 
    1748     for (i = 0; i < 8; ++i)
     1752static void lapicDumpVec(APICDeviceInfo *pDev, APICState *lapic, PCDBGFINFOHLP pHlp, unsigned start)
     1753{
     1754    for (unsigned i = 0; i < 8; ++i)
    17491755    {
    1750         val = apic_mem_readl(pDev, lapic, start + (i << 4));
     1756        uint32_t val;
     1757        apic_mem_readl(pDev, lapic, start + (i << 4), &val);
    17511758        pHlp->pfnPrintf(pHlp, "%08X", val);
    17521759    }
    … …  
    17611768
    17621769    pHlp->pfnPrintf(pHlp, "Local APIC at %08X:\n", lapic->apicbase);
    1763     val = apic_mem_readl(pDev, lapic, 0x20);
     1770    apic_mem_readl(pDev, lapic, 0x20, &val);
    17641771    pHlp->pfnPrintf(pHlp, "  LAPIC ID  : %08X\n", val);
    17651772    pHlp->pfnPrintf(pHlp, "    APIC ID = %02X\n", (val >> 24) & 0xff);
    1766     val = apic_mem_readl(pDev, lapic, 0x30);
     1773    apic_mem_readl(pDev, lapic, 0x30, &val);
    17671774    max_lvt = (val >> 16) & 0xff;
    17681775    pHlp->pfnPrintf(pHlp, "  APIC VER   : %08X\n", val);
    17691776    pHlp->pfnPrintf(pHlp, "    version  = %02X\n", val & 0xff);
    17701777    pHlp->pfnPrintf(pHlp, "    lvts     = %d\n", ((val >> 16) & 0xff) + 1);
    1771     val = apic_mem_readl(pDev, lapic, 0x80);
     1778    apic_mem_readl(pDev, lapic, 0x80, &val);
    17721779    pHlp->pfnPrintf(pHlp, "  TPR        : %08X\n", val);
    17731780    pHlp->pfnPrintf(pHlp, "    task pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
    1774     val = apic_mem_readl(pDev, lapic, 0xA0);
     1781    apic_mem_readl(pDev, lapic, 0xA0, &val);
    17751782    pHlp->pfnPrintf(pHlp, "  PPR        : %08X\n", val);
    17761783    pHlp->pfnPrintf(pHlp, "    cpu pri  = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
    1777     val = apic_mem_readl(pDev, lapic, 0xD0);
     1784    apic_mem_readl(pDev, lapic, 0xD0, &val);
    17781785    pHlp->pfnPrintf(pHlp, "  LDR       : %08X\n", val);
    17791786    pHlp->pfnPrintf(pHlp, "    log id  = %02X\n", (val >> 24) & 0xff);
    1780     val = apic_mem_readl(pDev, lapic, 0xE0);
     1787    apic_mem_readl(pDev, lapic, 0xE0, &val);
    17811788    pHlp->pfnPrintf(pHlp, "  DFR       : %08X\n", val);
    1782     val = apic_mem_readl(pDev, lapic, 0xF0);
     1789    apic_mem_readl(pDev, lapic, 0xF0, &val);
    17831790    pHlp->pfnPrintf(pHlp, "  SVR       : %08X\n", val);
    17841791    pHlp->pfnPrintf(pHlp, "    focus   = %s\n", val & (1 << 9) ? "check off" : "check on");
    … …  
    17931800    val = get_highest_priority_int(lapic->irr);
    17941801    pHlp->pfnPrintf(pHlp, "    highest = %02X\n", val == ~0U ? 0 : val);
    1795     val = apic_mem_readl(pDev, lapic, 0x320);
     1802    apic_mem_readl(pDev, lapic, 0x320, &val);
    17961803}
    17971804
    … …  
    17991806static DECLCALLBACK(void) lapicInfoLVT(APICDeviceInfo  *pDev, APICState *lapic, PCDBGFINFOHLP pHlp)
    18001807{
    1801     uint32_t        val;
    1802     static const char *dmodes[] = { "Fixed ", "Reserved", "SMI", "Reserved",
    1803                                     "NMI", "INIT", "Reserved", "ExtINT" };
    1804 
    1805     val = apic_mem_readl(pDev, lapic, 0x320);
     1808    static const char *s_apszDeliveryModes[] =
     1809    {
     1810        "Fixed ", "Reserved", "SMI", "Reserved", "NMI", "INIT", "Reserved", "ExtINT"
     1811    };
     1812    uint32_t val;
     1813
     1814    apic_mem_readl(pDev, lapic, 0x320, &val);
    18061815    pHlp->pfnPrintf(pHlp, "  LVT Timer : %08X\n", val);
    18071816    pHlp->pfnPrintf(pHlp, "    mode    = %s\n", val & (1 << 17) ? "periodic" : "one-shot");
    … …  
    18091818    pHlp->pfnPrintf(pHlp, "    status  = %s\n", val & (1 << 12) ? "pending" : "idle");
    18101819    pHlp->pfnPrintf(pHlp, "    vector  = %02X\n", val & 0xff);
    1811     val = apic_mem_readl(pDev, lapic, 0x350);
     1820    apic_mem_readl(pDev, lapic, 0x350, &val);
    18121821    pHlp->pfnPrintf(pHlp, "  LVT LINT0 : %08X\n", val);
    18131822    pHlp->pfnPrintf(pHlp, "    mask    = %d\n", (val >> 16) & 1);
    … …  
    18161825    pHlp->pfnPrintf(pHlp, "    polarty = %d\n", (val >> 13) & 1);
    18171826    pHlp->pfnPrintf(pHlp, "    status  = %s\n", val & (1 << 12) ? "pending" : "idle");
    1818     pHlp->pfnPrintf(pHlp, "    delivry = %s\n", dmodes[(val >> 8) & 7]);
     1827    pHlp->pfnPrintf(pHlp, "    delivry = %s\n", s_apszDeliveryModes[(val >> 8) & 7]);
    18191828    pHlp->pfnPrintf(pHlp, "    vector  = %02X\n", val & 0xff);
    1820     val = apic_mem_readl(pDev, lapic, 0x360);
     1829    apic_mem_readl(pDev, lapic, 0x360, &val);
    18211830    pHlp->pfnPrintf(pHlp, "  LVT LINT1 : %08X\n", val);
    18221831    pHlp->pfnPrintf(pHlp, "    mask    = %d\n", (val >> 16) & 1);
    … …  
    18251834    pHlp->pfnPrintf(pHlp, "    polarty = %d\n", (val >> 13) & 1);
    18261835    pHlp->pfnPrintf(pHlp, "    status  = %s\n", val & (1 << 12) ? "pending" : "idle");
    1827     pHlp->pfnPrintf(pHlp, "    delivry = %s\n", dmodes[(val >> 8) & 7]);
     1836    pHlp->pfnPrintf(pHlp, "    delivry = %s\n", s_apszDeliveryModes[(val >> 8) & 7]);
    18281837    pHlp->pfnPrintf(pHlp, "    vector  = %02X\n", val & 0xff);
    18291838}
    18301839
    18311840/* Print LAPIC timer state. */
    1832 static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo  *pDev, APICState *lapic, PCDBGFINFOHLP pHlp)
     1841static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo *pDev, APICState *lapic, PCDBGFINFOHLP pHlp)
    18331842{
    18341843    uint32_t        val;
    … …  
    18361845
    18371846    pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
    1838     val = apic_mem_readl(pDev, lapic, 0x380);
     1847    apic_mem_readl(pDev, lapic, 0x380, &val);
    18391848    pHlp->pfnPrintf(pHlp, "  Initial count : %08X\n", val);
    1840     val = apic_mem_readl(pDev, lapic, 0x390);
     1849    apic_mem_readl(pDev, lapic, 0x390, &val);
    18411850    pHlp->pfnPrintf(pHlp, "  Current count : %08X\n", val);
    1842     val = apic_mem_readl(pDev, lapic, 0x3E0);
     1851    apic_mem_readl(pDev, lapic, 0x3E0, &val);
    18431852    pHlp->pfnPrintf(pHlp, "  Divide config : %08X\n", val);
    18441853    divider = ((val >> 1) & 0x04) | (val & 0x03);
    … …  
    18611870
    18621871    if (pszArgs == NULL || !strcmp(pszArgs, "basic"))
    1863     {
    18641872        lapicInfoBasic(pDev, lapic, pHlp);
    1865     }
    18661873    else if (!strcmp(pszArgs, "lvt"))
    1867     {
    18681874        lapicInfoLVT(pDev, lapic, pHlp);
    1869     }
    18701875    else if (!strcmp(pszArgs, "timer"))
    1871     {
    18721876        lapicInfoTimer(pDev, lapic, pHlp);
    1873     }
    18741877    else
    1875     {
    18761878        pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
    1877     }
    18781879}
    18791880
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