Index: trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 39038)
+++ trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 39078)
@@ -402,6 +402,8 @@
     if (IOM_SUCCESS(rcStrict))
         pCtxCore->rip += cbOp;
+    NOREF(pVCpu);
     return rcStrict;
 #else
+    NOREF(pVM); NOREF(pVCpu); NOREF(pCtxCore); NOREF(pDis); NOREF(cbOp);
     AssertReleaseMsgFailed(("not implemented\n"));
     return VERR_NOT_IMPLEMENTED;
@@ -421,4 +423,6 @@
      * instruction and it either flushed the TLB or the CPU reused it.
      */
+#else
+    NOREF(pVM);
 #endif
     return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /*fMayTrap*/ false);
@@ -430,4 +434,5 @@
     /* Don't use MMGCRamWrite here as it does not respect zero pages, shared
        pages or write monitored pages. */
+    NOREF(pVM);
     return PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /*fMayTrap*/ false);
 }
@@ -508,4 +513,5 @@
 {
     OP_PARAMVAL param1, param2;
+    NOREF(pvFault);
 
     /* Source to make DISQueryParamVal read the register value - ugly hack */
@@ -642,4 +648,5 @@
 {
     OP_PARAMVAL param1;
+    NOREF(pvFault);
 
     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
@@ -711,4 +718,6 @@
     Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
     OP_PARAMVAL param1;
+    NOREF(pvFault);
+
     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
     if(RT_FAILURE(rc))
@@ -791,4 +800,5 @@
 {
     OP_PARAMVAL param1, param2;
+    NOREF(pvFault);
 
     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
@@ -887,4 +897,5 @@
     void *pvParam1;
     OP_PARAMVAL param1, param2;
+    NOREF(pvFault);
 
 #if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
@@ -958,4 +969,5 @@
                              PFNEMULATEPARAM3 pfnEmulate)
 {
+    NOREF(pvFault);
     OP_PARAMVAL param1, param2;
     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
@@ -1205,4 +1217,5 @@
 static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pvFault);
     OP_PARAMVAL param1, param2;
     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
@@ -1343,4 +1356,5 @@
     uint64_t cTransfers;
     int      offIncrement;
+    NOREF(pvFault);
 
     /* Don't support any but these three prefix bytes. */
@@ -1493,4 +1507,5 @@
 {
     OP_PARAMVAL param1, param2;
+    NOREF(pvFault);
 
 #if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
@@ -1564,4 +1579,5 @@
     Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
     OP_PARAMVAL param1;
+    NOREF(pvFault);
 
     /* Source to make DISQueryParamVal read the register value - ugly hack */
@@ -1619,4 +1635,5 @@
     void *pvParamReg2;
     size_t cbParamReg2;
+    NOREF(pvFault);
 
     /* Source to make DISQueryParamVal read the register value - ugly hack */
@@ -1746,4 +1763,5 @@
 {
     /* only allow direct calls to EMInterpretIret for now */
+    NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
     return VERR_EM_INTERPRETER;
 }
@@ -1755,4 +1773,5 @@
 {
     /* Nothing to do. */
+    NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
     return VINF_SUCCESS;
 }
@@ -1774,4 +1793,5 @@
      * (in absence of segment override prefixes)????
      */
+    NOREF(pVM); NOREF(pRegFrame);
 #ifdef IN_RC
     LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
@@ -1795,4 +1815,5 @@
     OP_PARAMVAL param1;
     RTGCPTR     addr;
+    NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
 
     VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
@@ -1843,4 +1864,5 @@
 {
     uint32_t iLeaf = pRegFrame->eax;
+    NOREF(pVM);
 
     /* cpuid clears the high dwords of the affected 64 bits registers. */
@@ -1862,4 +1884,5 @@
 static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
     int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
     return rc;
@@ -1883,4 +1906,5 @@
     int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
     AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
+    NOREF(pVM);
 
     if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
@@ -1909,4 +1933,5 @@
 VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
 {
+    NOREF(pVM);
     uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
     if (!(cr0 & X86_CR0_TS))
@@ -1920,4 +1945,5 @@
 static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretCLTS(pVM, pVCpu);
 }
@@ -1940,4 +1966,5 @@
     uint64_t msrEFER;
     int      rc, rc2;
+    NOREF(pVM);
 
     /** @todo Clean up this mess. */
@@ -2123,4 +2150,5 @@
     OP_PARAMVAL param1;
     uint32_t    val;
+    NOREF(pvFault); NOREF(pcbSize);
 
     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
@@ -2202,4 +2230,5 @@
 static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pvFault); NOREF(pcbSize);
     if ((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_CR)
         return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_ctrl);
@@ -2227,4 +2256,5 @@
     uint64_t val;
     int      rc;
+    NOREF(pVM);
 
     if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
@@ -2265,4 +2295,5 @@
 {
     uint64_t val64;
+    NOREF(pVM);
 
     int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
@@ -2288,4 +2319,5 @@
 {
     int rc = VERR_EM_INTERPRETER;
+    NOREF(pvFault); NOREF(pcbSize);
 
     if((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_DBG)
@@ -2312,4 +2344,5 @@
     OP_PARAMVAL param1;
     RTSEL       sel;
+    NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
 
     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
@@ -2360,4 +2393,5 @@
     RTGCPTR     pParam1;
     X86XDTR32   dtr32;
+    NOREF(pvFault); NOREF(pcbSize);
 
     Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
@@ -2404,4 +2438,5 @@
 static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pcbSize);
     PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
 
@@ -2430,4 +2465,5 @@
 emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
     return VINF_EM_HALT;
 }
@@ -2456,4 +2492,5 @@
     pRegFrame->rdx = (uTicks >> 32ULL);
 
+    NOREF(pVM);
     return VINF_SUCCESS;
 }
@@ -2498,4 +2535,5 @@
 static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
 }
@@ -2526,4 +2564,6 @@
     pRegFrame->rdx = 0;
     /** @todo We should trigger a #GP here if the cpu doesn't support the index in ecx. */
+
+    NOREF(pVM);
     return VINF_SUCCESS;
 }
@@ -2534,4 +2574,5 @@
 static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
 }
@@ -2543,4 +2584,5 @@
 {
     uint32_t u32Dummy, u32ExtFeatures, cpl;
+    NOREF(pVM);
 
     if (pRegFrame->ecx != 0)
@@ -2568,4 +2610,5 @@
 static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
 }
@@ -2578,4 +2621,5 @@
 {
     uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
+    NOREF(pVM);
 
     /* Get the current privilege level. */
@@ -2621,4 +2665,5 @@
 static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretMWait(pVM, pVCpu, pRegFrame);
 }
@@ -2734,4 +2779,5 @@
     /** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
      *  That version clears the high dwords of both RDX & RAX */
+    NOREF(pVM);
 
     /* Get the current privilege level. */
@@ -2761,4 +2807,5 @@
              different, so we play safe by completely disassembling the instruction. */
     Assert(!(pDis->prefix & PREFIX_REX));
+    NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
 }
@@ -2787,4 +2834,5 @@
     LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
              RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
+    NOREF(pVM);
     return rc;
 }
@@ -2796,4 +2844,5 @@
 static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
 {
+    NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
 }
