Changeset 39125 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Oct 27, 2011 10:40:17 AM (13 years ago)

Author:

vboxsync

Message:

IEM: Fixed some details in the AAM, SAHF and LAHF instruction emulation.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAll.cpp (modified) (1 diff)
• IEMAllCImpl.cpp.h (modified) (2 diffs)
• IEMAllInstructions.cpp.h (modified) (5 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -2165 +2165 @@
 {
     return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_MF, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
+}
+
+
+/**
+ * Macro for calling iemCImplRaiseDivideError().
+ *
+ * This enables us to add/remove arguments and force different levels of
+ * inlining as we wish.
+ *
+ * @return  Strict VBox status code.
+ */
+#define IEMOP_RAISE_DIVIDE_ERROR()          IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
+IEM_CIMPL_DEF_0(iemCImplRaiseDivideError)
+{
+    NOREF(cbInstr);
+    return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_DE, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
 }
 

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -2962 +2962 @@
  * Implements 'AAM'.
  *
- * @param   enmEffOpSize    The effective operand size.
+ * @param   bImm            The immediate operand. Cannot be 0.
  */
 IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
+    Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
 
     uint16_t const ax = pCtx->ax;
@@ -2979 +2980 @@
     return VINF_SUCCESS;
 }
+
 
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

@@ -7799 +7799 @@
     else
     {
-        uint16_t offSeg16; IEM_OPCODE_GET_NEXT_U16(&offSeg16);
+        uint16_t offSeg16; IEM_OPCODE_GET_NEXT_U16(&offSeg16); /** @todo add GET_NEXT_U16_ZX_U32 to reduce code size. */
         offSeg = offSeg16;
     }
@@ -7846 +7846 @@
     IEMOP_MNEMONIC("sahf");
     IEMOP_HLP_NO_LOCK_PREFIX();
-    IEMOP_HLP_NO_64BIT();
+    if (   pIemCpu->enmCpuMode == IEMMODE_64BIT
+        && !IEM_IS_AMD_CPUID_FEATURE_PRESENT_ECX(X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
+        return IEMOP_RAISE_INVALID_OPCODE();
     IEM_MC_BEGIN(0, 2);
     IEM_MC_LOCAL(uint32_t, u32Flags);
@@ -7852 +7854 @@
     IEM_MC_FETCH_EFLAGS(EFlags);
     IEM_MC_FETCH_GREG_U8_ZX_U32(u32Flags, X86_GREG_xSP/*=AH*/);
-    IEM_MC_AND_LOCAL_U32(u32Flags, UINT32_C(0xd7));
+    IEM_MC_AND_LOCAL_U32(u32Flags, X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
     IEM_MC_AND_LOCAL_U32(EFlags, UINT32_C(0xffffff00));
-    IEM_MC_OR_LOCAL_U32(u32Flags, UINT32_C(0x00000002));
+    IEM_MC_OR_LOCAL_U32(u32Flags, X86_EFL_1);
     IEM_MC_OR_2LOCS_U32(EFlags, u32Flags);
     IEM_MC_COMMIT_EFLAGS(EFlags);
@@ -7868 +7870 @@
     IEMOP_MNEMONIC("lahf");
     IEMOP_HLP_NO_LOCK_PREFIX();
-    IEMOP_HLP_NO_64BIT();
+    if (   pIemCpu->enmCpuMode == IEMMODE_64BIT
+        && !IEM_IS_AMD_CPUID_FEATURE_PRESENT_ECX(X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
+        return IEMOP_RAISE_INVALID_OPCODE();
     IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(uint8_t, u8Flags);
@@ -9863 +9867 @@
     IEMOP_HLP_NO_LOCK_PREFIX();
     IEMOP_HLP_NO_64BIT();
+    if (!bImm)
+        return IEMOP_RAISE_DIVIDE_ERROR();
     return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_aam, bImm);
 }