Changeset 39139 in vbox for trunk/src/VBox/Devices/USB
- Timestamp:
- Oct 28, 2011 2:30:37 PM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 74593
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/USB/DevOHCI.cpp
r39136 r39139 5 5 6 6 /* 7 * Copyright (C) 2006-20 09Oracle Corporation7 * Copyright (C) 2006-2011 Oracle Corporation 8 8 * 9 9 * This file is part of VirtualBox Open Source Edition (OSE), as … … 115 115 116 116 117 /* Number of Downstream Ports on the root hub, if you change this 118 * you need to add more status register words to the 'opreg' array 117 /** Number of Downstream Ports on the root hub. 118 * If you change this you need to add more status register words to the 'opreg' 119 * array. 119 120 */ 120 121 #define OHCI_NDP 8 … … 122 123 /** Pointer to OHCI device data. */ 123 124 typedef struct OHCI *POHCI; 125 /** Read-only pointer to the OHCI device data. */ 126 typedef struct OHCI const *PCOHCI; 124 127 125 128 … … 536 539 { 537 540 const char *pszName; 538 int (*pfnRead )(P OHCI ohci, uint32_t iReg, uint32_t *pu32Value);539 int (*pfnWrite)(POHCI ohci, uint32_t iReg, uint32_t u32Value);541 int (*pfnRead )(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value); 542 int (*pfnWrite)(POHCI pThis, uint32_t iReg, uint32_t u32Value); 540 543 } OHCIOPREG; 541 544 … … 3778 3781 * Read the HcRevision register. 3779 3782 */ 3780 static int HcRevision_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)3783 static int HcRevision_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 3781 3784 { 3782 3785 Log2(("HcRevision_r() -> 0x10\n")); … … 3798 3801 * Read the HcControl register. 3799 3802 */ 3800 static int HcControl_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)3803 static int HcControl_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 3801 3804 { 3802 3805 uint32_t ctl = pOhci->ctl; … … 3878 3881 * Read the HcCommandStatus register. 3879 3882 */ 3880 static int HcCommandStatus_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)3883 static int HcCommandStatus_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 3881 3884 { 3882 3885 uint32_t status = pOhci->status; … … 3929 3932 * Read the HcInterruptStatus register. 3930 3933 */ 3931 static int HcInterruptStatus_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)3934 static int HcInterruptStatus_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 3932 3935 { 3933 3936 uint32_t val = pOhci->intr_status; … … 3971 3974 * Read the HcInterruptEnable register 3972 3975 */ 3973 static int HcInterruptEnable_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)3976 static int HcInterruptEnable_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 3974 3977 { 3975 3978 uint32_t val = pOhci->intr; … … 4010 4013 * Reads the HcInterruptDisable register. 4011 4014 */ 4012 static int HcInterruptDisable_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4015 static int HcInterruptDisable_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4013 4016 { 4014 4017 #if 1 /** @todo r=bird: "On read, the current value of the HcInterruptEnable register is returned." */ … … 4054 4057 * Read the HcHCCA register (Host Controller Communications Area physical address). 4055 4058 */ 4056 static int HcHCCA_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4059 static int HcHCCA_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4057 4060 { 4058 4061 Log2(("HcHCCA_r() -> %#010x\n", pOhci->hcca)); … … 4074 4077 * Read the HcPeriodCurrentED register. 4075 4078 */ 4076 static int HcPeriodCurrentED_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4079 static int HcPeriodCurrentED_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4077 4080 { 4078 4081 Log2(("HcPeriodCurrentED_r() -> %#010x\n", pOhci->per_cur)); … … 4097 4100 * Read the HcControlHeadED register. 4098 4101 */ 4099 static int HcControlHeadED_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4102 static int HcControlHeadED_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4100 4103 { 4101 4104 Log2(("HcControlHeadED_r() -> %#010x\n", pOhci->ctrl_head)); … … 4118 4121 * Read the HcControlCurrentED register. 4119 4122 */ 4120 static int HcControlCurrentED_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4123 static int HcControlCurrentED_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4121 4124 { 4122 4125 Log2(("HcControlCurrentED_r() -> %#010x\n", pOhci->ctrl_cur)); … … 4140 4143 * Read the HcBulkHeadED register. 4141 4144 */ 4142 static int HcBulkHeadED_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4145 static int HcBulkHeadED_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4143 4146 { 4144 4147 Log2(("HcBulkHeadED_r() -> %#010x\n", pOhci->bulk_head)); … … 4161 4164 * Read the HcBulkCurrentED register. 4162 4165 */ 4163 static int HcBulkCurrentED_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4166 static int HcBulkCurrentED_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4164 4167 { 4165 4168 Log2(("HcBulkCurrentED_r() -> %#010x\n", pOhci->bulk_cur)); … … 4184 4187 * Read the HcDoneHead register. 4185 4188 */ 4186 static int HcDoneHead_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4189 static int HcDoneHead_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4187 4190 { 4188 4191 Log2(("HcDoneHead_r() -> 0x%#08x\n", pOhci->done)); … … 4205 4208 * Read the HcFmInterval (Fm=Frame) register. 4206 4209 */ 4207 static int HcFmInterval_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4210 static int HcFmInterval_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4208 4211 { 4209 4212 uint32_t val = (pOhci->fit << 31) | (pOhci->fsmps << 16) | (pOhci->fi); … … 4242 4245 * Read the HcFmRemaining (Fm = Frame) register. 4243 4246 */ 4244 static int HcFmRemaining_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4247 static int HcFmRemaining_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4245 4248 { 4246 4249 uint32_t Value = pOhci->frt << 31; … … 4278 4281 * Read the HcFmNumber (Fm = Frame) register. 4279 4282 */ 4280 static int HcFmNumber_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4283 static int HcFmNumber_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4281 4284 { 4282 4285 uint32_t val = (uint16_t)pOhci->HcFmNumber; … … 4300 4303 * The register determines when in a frame to switch from control&bulk to periodic lists. 4301 4304 */ 4302 static int HcPeriodicStart_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4305 static int HcPeriodicStart_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4303 4306 { 4304 4307 Log2(("HcPeriodicStart_r() -> %#010x - PS=%d\n", pOhci->pstart, pOhci->pstart & 0x3fff)); … … 4323 4326 * Read the HcLSThreshold register. 4324 4327 */ 4325 static int HcLSThreshold_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4328 static int HcLSThreshold_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4326 4329 { 4327 4330 Log2(("HcLSThreshold_r() -> %#010x\n", OHCI_LS_THRESH)); … … 4353 4356 * Read the HcRhDescriptorA register. 4354 4357 */ 4355 static int HcRhDescriptorA_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4358 static int HcRhDescriptorA_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4356 4359 { 4357 4360 uint32_t val = pOhci->RootHub.desc_a; … … 4401 4404 * Read the HcRhDescriptorB register. 4402 4405 */ 4403 static int HcRhDescriptorB_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4406 static int HcRhDescriptorB_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4404 4407 { 4405 4408 uint32_t val = pOhci->RootHub.desc_b; … … 4432 4435 * Read the HcRhStatus (Rh = Root Hub) register. 4433 4436 */ 4434 static int HcRhStatus_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4437 static int HcRhStatus_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4435 4438 { 4436 4439 uint32_t val = pOhci->RootHub.status; … … 4505 4508 * Read the HcRhPortStatus register of a port. 4506 4509 */ 4507 static int HcRhPortStatus_r(P OHCI pOhci, uint32_t iReg, uint32_t *pu32Value)4510 static int HcRhPortStatus_r(PCOHCI pOhci, uint32_t iReg, uint32_t *pu32Value) 4508 4511 { 4509 4512 const unsigned i = iReg - 21; … … 4790 4793 POHCI pOhci = PDMINS_2_DATA(pDevIns, POHCI); 4791 4794 4792 /* 4793 * Validate the access. 4794 */ 4795 if (cb != sizeof(uint32_t)) 4796 { 4797 Log2(("ohciRead: Bad read size!!! GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb)); 4798 return VINF_IOM_MMIO_UNUSED_FF; /* No idea what really would happen... */ 4799 } 4800 if (GCPhysAddr & 0x3) 4801 { 4802 Log2(("ohciRead: Unaligned read!!! GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb)); 4803 return VINF_IOM_MMIO_UNUSED_FF; 4804 } 4795 /* Paranoia: Assert that IOMMMIO_FLAGS_READ_DWORD works. */ 4796 AssertReturn(cb != sizeof(uint32_t), VERR_INTERNAL_ERROR_3); 4797 AssertReturn(!(GCPhysAddr & 0x3), VERR_INTERNAL_ERROR_4); 4805 4798 4806 4799 /* … … 4873 4866 #ifdef IN_RING3 4874 4867 4875 static DECLCALLBACK(int) 4876 ohciR3Map(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType) 4868 /** 4869 * @callback_method_impl{FNPCIIOREGIONMAP} 4870 */ 4871 static DECLCALLBACK(int) ohciR3Map(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType) 4877 4872 { 4878 4873 POHCI pOhci = (POHCI)pPciDev; 4879 4874 int rc = PDMDevHlpMMIORegister(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, NULL /*pvUser*/, 4880 IOMMMIO_FLAGS_READ_ PASSTHRU| IOMMMIO_FLAGS_WRITE_PASSTHRU,4875 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU, 4881 4876 ohciWrite, ohciRead, "USB OHCI"); 4882 4877 if (RT_FAILURE(rc)) … … 4888 4883 return rc; 4889 4884 4890 rc = PDMDevHlpMMIORegisterR0(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/, 4891 "ohciWrite", "ohciRead"); 4885 rc = PDMDevHlpMMIORegisterR0(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/, "ohciWrite", "ohciRead"); 4892 4886 if (RT_FAILURE(rc)) 4893 4887 return rc; 4894 4895 4888 # endif 4896 4889 … … 4898 4891 return VINF_SUCCESS; 4899 4892 } 4893 4900 4894 4901 4895 /** … … 4945 4939 return VINF_SUCCESS; 4946 4940 } 4941 4947 4942 4948 4943 /**
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