Changeset 39154 in vbox for trunk/src/VBox/Devices/USB
- Timestamp:
- Oct 31, 2011 3:36:29 PM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 74616
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/USB/DevOHCI.cpp
r39151 r39154 351 351 /** A flag indicating that the bulk list may have in-flight URBs. */ 352 352 bool fBulkNeedsCleaning; 353 354 /** Whether RC/R0 is enabled. */ 355 bool fRZEnabled; 353 356 354 357 uint32_t Alignment3; /**< Align size on a 8 byte boundary. */ … … 4790 4793 * @param cb The size of the read. 4791 4794 */ 4792 PDMBOTHCBDECL(int) ohci Read(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)4795 PDMBOTHCBDECL(int) ohciMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb) 4793 4796 { 4794 4797 POHCI pOhci = PDMINS_2_DATA(pDevIns, POHCI); … … 4829 4832 * @param cb The size of the data being written. 4830 4833 */ 4831 PDMBOTHCBDECL(int) ohci Write(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)4834 PDMBOTHCBDECL(int) ohciMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb) 4832 4835 { 4833 4836 POHCI pOhci = PDMINS_2_DATA(pDevIns, POHCI); … … 4838 4841 if (cb != sizeof(uint32_t)) 4839 4842 { 4840 Log2(("ohci Write: Bad write size!!! GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb));4843 Log2(("ohciMmioWrite: Bad write size!!! GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb)); 4841 4844 return VINF_SUCCESS; 4842 4845 } 4843 4846 if (GCPhysAddr & 0x3) 4844 4847 { 4845 Log2(("ohci Write: Unaligned write!!! GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb));4848 Log2(("ohciMmioWrite: Unaligned write!!! GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb)); 4846 4849 return VINF_SUCCESS; 4847 4850 } … … 4874 4877 POHCI pOhci = (POHCI)pPciDev; 4875 4878 int rc = PDMDevHlpMMIORegister(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, NULL /*pvUser*/, 4876 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU, 4877 ohciWrite, ohciRead, "USB OHCI"); 4879 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED 4880 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE, 4881 ohciMmioWrite, ohciMmioRead, "USB OHCI"); 4878 4882 if (RT_FAILURE(rc)) 4879 4883 return rc; 4880 4884 4881 # if 1 /* this enabled / disabled GC/R0 stuff */ 4882 rc = PDMDevHlpMMIORegisterRC(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/, "ohciWrite", "ohciRead"); 4883 if (RT_FAILURE(rc)) 4884 return rc; 4885 4886 rc = PDMDevHlpMMIORegisterR0(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/, "ohciWrite", "ohciRead"); 4887 if (RT_FAILURE(rc)) 4888 return rc; 4889 # endif 4885 if (pOhci->fRZEnabled) 4886 { 4887 rc = PDMDevHlpMMIORegisterRC(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, 4888 NIL_RTRCPTR /*pvUser*/, "ohciMmioWrite", "ohciMmioRead"); 4889 if (RT_FAILURE(rc)) 4890 return rc; 4891 4892 rc = PDMDevHlpMMIORegisterR0(pOhci->CTX_SUFF(pDevIns), GCPhysAddress, cb, 4893 NIL_RTR0PTR /*pvUser*/, "ohciMmioWrite", "ohciMmioRead"); 4894 if (RT_FAILURE(rc)) 4895 return rc; 4896 } 4890 4897 4891 4898 pOhci->MMIOBase = GCPhysAddress; … … 5366 5373 static DECLCALLBACK(int) ohciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 5367 5374 { 5368 POHCI pOhci = PDMINS_2_DATA(pDevIns, POHCI); 5369 int rc; 5375 POHCI pOhci = PDMINS_2_DATA(pDevIns, POHCI); 5370 5376 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 5371 5372 /*5373 * Read configuration. No configuration keys are currently supported.5374 */5375 if (!CFGMR3AreValuesValid(pCfg, "\0"))5376 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,5377 N_("Configuration error: Unknown config key"));5378 5377 5379 5378 /* … … 5409 5408 pOhci->RootHub.ILeds.pfnQueryStatusLed = ohciRhQueryStatusLed; 5410 5409 5410 5411 /* 5412 * Read configuration. No configuration keys are currently supported. 5413 */ 5414 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RZEnabled", ""); 5415 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pOhci->fRZEnabled, true); 5416 AssertLogRelRCReturn(rc, rc); 5417 5418 5411 5419 /* 5412 5420 * Register PCI device and I/O region. … … 5423 5431 aMsiReg.iMsiNextOffset = 0x0; 5424 5432 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg); 5425 if (RT_FAILURE 5433 if (RT_FAILURE(rc)) 5426 5434 { 5427 5435 PCIDevSetCapabilityList(&pOhci->PciDev, 0x0);
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