Changeset 40001 in vbox for trunk/src/VBox/VMM/testcase

Timestamp:

Feb 5, 2012 9:30:40 PM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

76112

Message:

IEM: Filled in some NOPs and PREFETCHes.

Location:

trunk/src/VBox/VMM/testcase

Files:

• tstIEMCheckMc.cpp (modified) (1 diff)
• tstX86-1.cpp (modified) (2 diffs)
• tstX86-1A.asm (modified) (1 diff)

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -112 +112 @@
 #define IEM_IS_REAL_MODE(a_pIemCpu)                         (g_fRandom)
 #define IEM_IS_AMD_CPUID_FEATURE_PRESENT_ECX(a_fEcx)        (g_fRandom)
+#define IEM_IS_AMD_CPUID_FEATURE_PRESENT_EDX(a_fEdx)        (g_fRandom)
+#define IEM_IS_AMD_CPUID_FEATURES_ANY_PRESENT(a_fEdx, a_fEcx) (g_fRandom)
 #define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(a_fEdx)      (g_fRandom)
 

trunk/src/VBox/VMM/testcase/tstX86-1.cpp

@@ -69 +69 @@
 DECLASM(int32_t) x861_Test2(void);
 DECLASM(int32_t) x861_Test3(void);
+DECLASM(int32_t) x861_Test4(void);
 
 
@@ -227 +228 @@
             RTTestFailed(hTest, "x861_Test2 -> %d", rc);
 
-#endif
         RTTestSub(hTest, "fxsave / fxrstor and #PFs");
         rc = x861_Test3();
         if (rc != 0)
             RTTestFailed(hTest, "x861_Test3 -> %d", rc);
+#endif
+        RTTestSub(hTest, "Multibyte NOPs");
+        rc = x861_Test4();
+        if (rc != 0)
+            RTTestFailed(hTest, "x861_Test4 -> %d", rc);
     }
 

trunk/src/VBox/VMM/testcase/tstX86-1A.asm

@@ -1219 +1219 @@
 
 ;;
+; Tests various multibyte NOP sequences.
+;
+BEGINPROC   x861_Test4
+        SAVE_ALL_PROLOGUE
+        call    x861_ClearRegisters
+
+        ; Intel recommended sequences.
+        nop
+        db 066h, 090h
+        db 00fh, 01fh, 000h
+        db 00fh, 01fh, 040h, 000h
+        db 00fh, 01fh, 044h, 000h, 000h
+        db 066h, 00fh, 01fh, 044h, 000h, 000h
+        db 00fh, 01fh, 080h, 000h, 000h, 000h, 000h
+        db 00fh, 01fh, 084h, 000h, 000h, 000h, 000h, 000h
+        db 066h, 00fh, 01fh, 084h, 000h, 000h, 000h, 000h, 000h
+
+        ; Check that the NOPs are allergic to lock prefixing.
+        ShouldTrap X86_XCPT_UD, db 0f0h, 090h               ; lock prefixed NOP.
+        ShouldTrap X86_XCPT_UD, db 0f0h, 066h, 090h         ; lock prefixed two byte NOP.
+        ShouldTrap X86_XCPT_UD, db 0f0h, 00fh, 01fh, 000h   ; lock prefixed three byte NOP.
+
+        ; Check the range of instructions that AMD marks as NOPs.
+%macro TST_NOP 1
+        db 00fh, %1, 000h
+        db 00fh, %1, 040h, 000h
+        db 00fh, %1, 044h, 000h, 000h
+        db 066h, 00fh, %1, 044h, 000h, 000h
+        db 00fh, %1, 080h, 000h, 000h, 000h, 000h
+        db 00fh, %1, 084h, 000h, 000h, 000h, 000h, 000h
+        db 066h, 00fh, %1, 084h, 000h, 000h, 000h, 000h, 000h
+        ShouldTrap X86_XCPT_UD, db 0f0h, 00fh, %1, 000h
+%endmacro
+        TST_NOP 019h
+        TST_NOP 01ah
+        TST_NOP 01bh
+        TST_NOP 01ch
+        TST_NOP 01dh
+        TST_NOP 01eh
+        TST_NOP 01fh
+
+        ; The AMD P group, intel marks this as a NOP.
+        TST_NOP 00dh
+
+.success:
+        xor     eax, eax
+.return:
+        SAVE_ALL_EPILOGUE
+        ret
+ENDPROC     x861_Test4
+
+;;
 ; Terminate the trap info array with a NIL entry.
 BEGINDATA