Changeset 40022 in vbox for trunk

Timestamp:

Feb 7, 2012 8:29:04 PM (13 years ago)

Author:

vboxsync

Message:

IEM: fxsave & fxrstor.

Location:

trunk

Files:

• include/VBox/vmm/vm.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (4 diffs)
• src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h (modified) (2 diffs)
• src/VBox/VMM/include/IEMInternal.h (modified) (1 diff)

trunk/include/VBox/vmm/vm.h

@@ -156 +156 @@
         struct IEMCPU       s;
 #endif
-        uint8_t             padding[1024];      /* multiple of 64 */
+        uint8_t             padding[3072];      /* multiple of 64 */
     } iem;
 
@@ -215 +215 @@
 
     /** Align the following members on page boundary. */
-    uint8_t                 abAlignment2[3072];
+    uint8_t                 abAlignment2[1024];
 
     /** PGM part. */

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -569 +569 @@
 static VBOXSTRICTRC     iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);
 static VBOXSTRICTRC     iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc);
+static VBOXSTRICTRC     iemRaiseAlignmentCheckException(PIEMCPU pIemCpu);
 static VBOXSTRICTRC     iemMemMap(PIEMCPU pIemCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess);
 static VBOXSTRICTRC     iemMemCommitAndUnmap(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess);
@@ -2366 +2367 @@
 
 
-/** \#MF(n) - 10.  */
+/** \#MF(0) - 10.  */
 DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseMathFault(PIEMCPU pIemCpu)
 {
     return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_MF, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
+}
+
+
+/** \#AC(0) - 11.  */
+DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseAlignmentCheckException(PIEMCPU pIemCpu)
+{
+    return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_AC, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
 }
 
@@ -3859 +3867 @@
  *                              memory.
  * @param   cbMem               The number of bytes to map.  This is usually 1,
- *                              2, 4, 6, 8, 12, 16 or 32.  When used by string
- *                              operations it can be up to a page.
+ *                              2, 4, 6, 8, 12, 16, 32 or 512.  When used by
+ *                              string operations it can be up to a page.
  * @param   iSegReg             The index of the segment register to use for
  *                              this access.  The base and limits are checked.
@@ -3877 +3885 @@
      * Check the input and figure out which mapping entry to use.
      */
-    Assert(cbMem <= 32);
+    Assert(cbMem <= 32 || cbMem == 512);
     Assert(~(fAccess & ~(IEM_ACCESS_TYPE_MASK | IEM_ACCESS_WHAT_MASK)));
 

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -3303 +3303 @@
  * Implements 'FXSAVE'.
  *
+ * @param   iEffSeg         The effective segment.
  * @param   GCPtrEff        The address of the image.
  * @param   enmEffOpSize    The operand size (only REX.W really matters).
  */
-IEM_CIMPL_DEF_2(iemCImpl_fxsave, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
+IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
 
+    /*
+     * Raise exceptions.
+     */
+    if (pCtx->cr0 & X86_CR0_EM)
+        return iemRaiseUndefinedOpcode(pIemCpu);
     if (pCtx->cr0 & (X86_CR0_TS | X86_CR0_EM))
         return iemRaiseDeviceNotAvailable(pIemCpu);
-    if (GCPtrEff & 15) /** @todo \#AC */
+    if (GCPtrEff & 15)
+    {
+        /** @todo CPU/VM detection possible! \#AC might not be signal for
+         * all/any misalignment sizes, intel says its an implementation detail. */
+        if (   (pCtx->cr0 & X86_CR0_AM)
+            && pCtx->eflags.Bits.u1AC
+            && pIemCpu->uCpl == 3)
+            return iemRaiseAlignmentCheckException(pIemCpu);
         return iemRaiseGeneralProtectionFault0(pIemCpu);
-
-
-    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
+    }
+    AssertReturn(iemFRegIsFxSaveFormat(pIemCpu), VERR_IEM_IPE_2);
+
+    /*
+     * Access the memory.
+     */
+    void *pvMem512;
+    VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W);
+    if (rcStrict != VINF_SUCCESS)
+        return rcStrict;
+    PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
+
+    /*
+     * Store the registers.
+     */
+    /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
+     * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
+
+    /* common for all formats */
+    pDst->FCW           = pCtx->fpu.FCW;
+    pDst->FSW           = pCtx->fpu.FSW;
+    pDst->FTW           = pCtx->fpu.FTW & UINT16_C(0xff);
+    pDst->FOP           = pCtx->fpu.FOP;
+    pDst->MXCSR         = pCtx->fpu.MXCSR;
+    pDst->MXCSR_MASK    = pCtx->fpu.MXCSR_MASK;
+    for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
+    {
+        /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
+         *        them for now... */
+        pDst->aRegs[i].au32[0] = pCtx->fpu.aRegs[i].au32[0];
+        pDst->aRegs[i].au32[1] = pCtx->fpu.aRegs[i].au32[1];
+        pDst->aRegs[i].au32[2] = pCtx->fpu.aRegs[i].au32[2] & UINT32_C(0xffff);
+        pDst->aRegs[i].au32[3] = 0;
+    }
+
+    /* FPU IP, CS, DP and DS. */
+    /** @todo FPU IP, CS, DP and DS cannot be implemented correctly without extra
+     * state information. :-/
+     * Storing zeros now to prevent any potential leakage of host info. */
+    pDst->FPUIP  = 0;
+    pDst->CS     = 0;
+    pDst->Rsrvd1 = 0;
+    pDst->FPUDP  = 0;
+    pDst->DS     = 0;
+    pDst->Rsrvd2 = 0;
+
+    /* XMM registers. */
+    if (   !(pCtx->msrEFER & MSR_K6_EFER_FFXSR)
+        || pIemCpu->enmCpuMode != IEMMODE_64BIT
+        || pIemCpu->uCpl != 0)
+    {
+        uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
+        for (uint32_t i = 0; i < cXmmRegs; i++)
+            pDst->aXMM[i] = pCtx->fpu.aXMM[i];
+        /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
+         *        right? */
+    }
+
+    /*
+     * Commit the memory.
+     */
+    rcStrict = iemMemCommitAndUnmap(pIemCpu, pvMem512, IEM_ACCESS_DATA_W);
+    if (rcStrict != VINF_SUCCESS)
+        return rcStrict;
+
+    iemRegAddToRip(pIemCpu, cbInstr);
+    return VINF_SUCCESS;
 }
 
@@ -3326 +3403 @@
  * @param   enmEffOpSize    The operand size (only REX.W really matters).
  */
-IEM_CIMPL_DEF_2(iemCImpl_fxrstor, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
+IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
 
+    /*
+     * Raise exceptions.
+     */
+    if (pCtx->cr0 & X86_CR0_EM)
+        return iemRaiseUndefinedOpcode(pIemCpu);
     if (pCtx->cr0 & (X86_CR0_TS | X86_CR0_EM))
         return iemRaiseDeviceNotAvailable(pIemCpu);
-    if (GCPtrEff & 15) /** @todo \#AC */
+    if (GCPtrEff & 15)
+    {
+        /** @todo CPU/VM detection possible! \#AC might not be signal for
+         * all/any misalignment sizes, intel says its an implementation detail. */
+        if (   (pCtx->cr0 & X86_CR0_AM)
+            && pCtx->eflags.Bits.u1AC
+            && pIemCpu->uCpl == 3)
+            return iemRaiseAlignmentCheckException(pIemCpu);
         return iemRaiseGeneralProtectionFault0(pIemCpu);
-
-
-    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
+    }
+    AssertReturn(iemFRegIsFxSaveFormat(pIemCpu), VERR_IEM_IPE_2);
+
+    /*
+     * Access the memory.
+     */
+    void *pvMem512;
+    VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
+    if (rcStrict != VINF_SUCCESS)
+        return rcStrict;
+    PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
+
+    /*
+     * Check the state for stuff which will GP(0).
+     */
+    uint32_t const fMXCSR      = pSrc->MXCSR;
+    uint32_t const fMXCSR_MASK = pCtx->fpu.MXCSR_MASK ? pCtx->fpu.MXCSR_MASK : UINT32_C(0xffbf);
+    if (fMXCSR & ~fMXCSR_MASK)
+    {
+        Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
+        return iemRaiseGeneralProtectionFault0(pIemCpu);
+    }
+
+    /*
+     * Load the registers.
+     */
+    /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
+     * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
+
+    /* common for all formats */
+    pCtx->fpu.FCW       = pSrc->FCW;
+    pCtx->fpu.FSW       = pSrc->FSW;
+    pCtx->fpu.FTW       = pSrc->FTW & UINT16_C(0xff);
+    pCtx->fpu.FOP       = pSrc->FOP;
+    pCtx->fpu.MXCSR     = fMXCSR;
+    /* (MXCSR_MASK is read-only) */
+    for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
+    {
+        pCtx->fpu.aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
+        pCtx->fpu.aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
+        pCtx->fpu.aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
+        pCtx->fpu.aRegs[i].au32[3] = 0;
+    }
+
+    /* FPU IP, CS, DP and DS. */
+    if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
+    {
+        pCtx->fpu.FPUIP  = pSrc->FPUIP;
+        pCtx->fpu.CS     = pSrc->CS;
+        pCtx->fpu.Rsrvd1 = pSrc->Rsrvd1;
+        pCtx->fpu.FPUDP  = pSrc->FPUDP;
+        pCtx->fpu.DS     = pSrc->DS;
+        pCtx->fpu.Rsrvd2 = pSrc->Rsrvd2;
+    }
+    else
+    {
+        pCtx->fpu.FPUIP  = pSrc->FPUIP;
+        pCtx->fpu.CS     = pSrc->CS;
+        pCtx->fpu.Rsrvd1 = 0;
+        pCtx->fpu.FPUDP  = pSrc->FPUDP;
+        pCtx->fpu.DS     = pSrc->DS;
+        pCtx->fpu.Rsrvd2 = 0;
+    }
+
+    /* XMM registers. */
+    if (   !(pCtx->msrEFER & MSR_K6_EFER_FFXSR)
+        || pIemCpu->enmCpuMode != IEMMODE_64BIT
+        || pIemCpu->uCpl != 0)
+    {
+        uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
+        for (uint32_t i = 0; i < cXmmRegs; i++)
+            pCtx->fpu.aXMM[i] = pSrc->aXMM[i];
+    }
+
+    /*
+     * Commit the memory.
+     */
+    rcStrict = iemMemCommitAndUnmap(pIemCpu, pvMem512, IEM_ACCESS_DATA_R);
+    if (rcStrict != VINF_SUCCESS)
+        return rcStrict;
+
+    iemRegAddToRip(pIemCpu, cbInstr);
+    return VINF_SUCCESS;
 }
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

@@ -3369 +3369 @@
         return IEMOP_RAISE_INVALID_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(2, 1);
-    IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                0);
-    IEM_MC_ARG_CONST(IEMMODE,   enmEffOpSize,/*=*/pIemCpu->enmEffOpSize, 1);
+    IEM_MC_BEGIN(3, 1);
+    IEM_MC_ARG_CONST(uint8_t,   iEffSeg,/*=*/pIemCpu->iEffSeg,           0);
+    IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
+    IEM_MC_ARG_CONST(IEMMODE,   enmEffOpSize,/*=*/pIemCpu->enmEffOpSize, 2);
     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm);
-    IEM_MC_CALL_CIMPL_2(iemCImpl_fxsave, GCPtrEff, enmEffOpSize);
+    IEM_MC_CALL_CIMPL_3(iemCImpl_fxsave, iEffSeg, GCPtrEff, enmEffOpSize);
     IEM_MC_END();
     return VINF_SUCCESS;
@@ -3387 +3388 @@
         return IEMOP_RAISE_INVALID_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(2, 1);
-    IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                0);
-    IEM_MC_ARG_CONST(IEMMODE,   enmEffOpSize,/*=*/pIemCpu->enmEffOpSize, 1);
+    IEM_MC_BEGIN(3, 1);
+    IEM_MC_ARG_CONST(uint8_t,   iEffSeg,/*=*/pIemCpu->iEffSeg,           0);
+    IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
+    IEM_MC_ARG_CONST(IEMMODE,   enmEffOpSize,/*=*/pIemCpu->enmEffOpSize, 2);
     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm);
-    IEM_MC_CALL_CIMPL_2(iemCImpl_fxrstor, GCPtrEff, enmEffOpSize);
+    IEM_MC_CALL_CIMPL_3(iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize);
     IEM_MC_END();
     return VINF_SUCCESS;

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -266 +266 @@
     struct
     {
-        uint8_t             ab[64];
+        uint8_t             ab[512];
     } aBounceBuffers[3];