Changeset 40024 in vbox for trunk

Timestamp:

Feb 7, 2012 9:50:43 PM (13 years ago)

Author:

vboxsync

Message:

IEM: Some more FPU work underways.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstructions.cpp.h (modified) (2 diffs)
• testcase/tstX86-1.cpp (modified) (3 diffs)
• testcase/tstX86-1A.asm (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

@@ -10003 +10003 @@
         case 5: pImpl = &g_iemAImpl_shr; IEMOP_MNEMONIC("shr Eb,CL"); break;
         case 7: pImpl = &g_iemAImpl_sar; IEMOP_MNEMONIC("sar Eb,CL"); break;
-        case 6: return IEMOP_RAISE_INVALID_LOCK_PREFIX();
+        case 6: return IEMOP_RAISE_INVALID_OPCODE();
         IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc, grr. */
     }
@@ -10383 +10383 @@
 /** Opcode 0xdc. */
 FNIEMOP_STUB(iemOp_EscF4);
+
+#if 0
+/** Opcode 0xdd /0 mem32real */
+FNIEMOP_STUB_1(iemOp_fld_m32r, uint8_t, bRm);
+
+/** Opcode 0xdd /0 stN */
+FNIEMOP_STUB_1(iemOp_fld_stN, uint8_t, bRm);
+
+/** Opcode 0xdd /1 stN   */
+FNIEMOP_STUB_1(iemOp_fst_m32r, uint8_t, bRm);
+
+/** Opcode 0xdd /2 mem32real */
+FNIEMOP_STUB_1(iemOp_fst_m32r, uint8_t, bRm);
+
+/** Opcode 0xdd /3 */
+FNIEMOP_STUB_1(iemOp_fstp_m32r, uint8_t, bRm);
+
+/** Opcode 0xdd /4 */
+FNIEMOP_STUB_1(iemOp_fldenv, uint8_t, bRm);
+
+/** Opcode 0xdd /5 */
+FNIEMOP_STUB_1(iemOp_fldcw, uint8_t, bRm);
+
+/** Opcode 0xdd /6 */
+FNIEMOP_STUB_1(iemOp_fstenv, uint8_t, bRm);
+
+/** Opcode 0xdd /7 */
+FNIEMOP_STUB_1(iemOp_fstcw, uint8_t, bRm);
+
+/** Opcode 0xdd 0xc9, 0xdd 0xd8-0xdf.  */
+FNIEMOP_STUB(iemOp_fnop);
+
+
 /** Opcode 0xdd. */
+FNIEMOP_DEF(iemOp_EscF5)
+{
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
+    {
+        switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
+        {
+            case 0: return FNIEMOP_CALL_1(iemOp_fld_stX,  bRm);
+            case 1: return FNIEMOP_CALL_1(iemOp_fxch_stX,  bRm);
+            case 2:
+                if (bRm == 0xc9)
+                    return FNIEMOP_CALL(iemOp_fnop);
+                return IEMOP_RAISE_INVALID_OPCODE();
+            case 3: return FNIEMOP_CALL(iemOp_fnop); /* AMD says reserved; tests on intel indicates FNOP. */
+            case 4:
+            case 5:
+            case 6:
+            case 7:
+            IEM_NOT_REACHED_DEFAULT_CASE_RET();
+        }
+
+    }
+    else
+    {
+        switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
+        {
+            case 0: return FNIEMOP_CALL_1(iemOp_fld_m32r,  bRm);
+            case 1: return IEMOP_RAISE_INVALID_OPCODE(); /** @todo Check if 0xdd /1 is a valid instruction which does/did something. */
+            case 2: return FNIEMOP_CALL_1(iemOp_fst_m32r,  bRm);
+            case 3: return FNIEMOP_CALL_1(iemOp_fstp_m32r, bRm);
+            case 4: return FNIEMOP_CALL_1(iemOp_fldenv,   bRm);
+            case 5: return FNIEMOP_CALL_1(iemOp_fldcw,    bRm);
+            case 6: return FNIEMOP_CALL_1(iemOp_fstenv,   bRm);
+            case 7: return FNIEMOP_CALL_1(iemOp_fstcw,    bRm);
+            IEM_NOT_REACHED_DEFAULT_CASE_RET();
+        }
+    }
+}
+#else
 FNIEMOP_STUB(iemOp_EscF5);
+#endif
+
 
 /** Opcode 0xde 0xd9. */

trunk/src/VBox/VMM/testcase/tstX86-1.cpp

@@ -70 +70 @@
 DECLASM(int32_t) x861_Test3(void);
 DECLASM(int32_t) x861_Test4(void);
+DECLASM(int32_t) x861_Test5(void);
 
 
@@ -217 +218 @@
          */
         int32_t rc;
-#if 1
+#if 0
         RTTestSub(hTest, "Misc 1");
         rc = x861_Test1();
@@ -232 +233 @@
         if (rc != 0)
             RTTestFailed(hTest, "x861_Test3 -> %d", rc);
-#endif
         RTTestSub(hTest, "Multibyte NOPs");
         rc = x861_Test4();
         if (rc != 0)
             RTTestFailed(hTest, "x861_Test4 -> %d", rc);
+        RTTestSub(hTest, "Odd floating point encodings");
+#endif
+        rc = x861_Test5();
+        if (rc != 0)
+            RTTestFailed(hTest, "x861_Test5 -> %d", rc);
     }
 

trunk/src/VBox/VMM/testcase/tstX86-1A.asm

@@ -1277 +1277 @@
 ENDPROC     x861_Test4
 
+
+
+;;
+; Tests some odd floating point instruction encodings.
+;
+BEGINPROC   x861_Test5
+        SAVE_ALL_PROLOGUE
+
+        ; standard stuff...
+        fld dword [.r32V1]
+        fld qword [.r64V1]
+        fld tword [.r80V1]
+
+        ShouldTrap X86_XCPT_UD, db 0d9h, 008h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 009h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 00ah
+        ShouldTrap X86_XCPT_UD, db 0d9h, 00bh
+        ShouldTrap X86_XCPT_UD, db 0d9h, 00ch
+        ShouldTrap X86_XCPT_UD, db 0d9h, 00dh
+        ShouldTrap X86_XCPT_UD, db 0d9h, 00eh
+        ShouldTrap X86_XCPT_UD, db 0d9h, 00fh
+
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0d1h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0d2h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0d3h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0d4h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0d5h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0d6h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0d7h
+        db 0d9h, 0d8h ; fnop?
+        db 0d9h, 0d9h ; fnop?
+        db 0d9h, 0dah ; fnop?
+        db 0d9h, 0dbh ; fnop?
+        db 0d9h, 0dch ; fnop?
+        db 0d9h, 0ddh ; fnop?
+        db 0d9h, 0deh ; fnop?
+        db 0d9h, 0dfh ; fnop?
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0e2h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0e3h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0e6h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0e7h
+        ShouldTrap X86_XCPT_UD, db 0d9h, 0efh
+
+
+.success:
+        xor     eax, eax
+.return:
+        SAVE_ALL_EPILOGUE
+        ret
+
+.r32V1: dd 3.2
+.r64V1: dq 6.4
+.r80V1: dt 8.0
+
+ENDPROC     x861_Test5
+
+
 ;;
 ; Terminate the trap info array with a NIL entry.