Changeset 40076 in vbox for trunk/include

Timestamp:

Feb 11, 2012 2:48:43 AM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

76210

Message:

Changed the types of the r80 views of the FPU registers.

Location:

trunk/include

Files:

• VBox/vmm/dbgf.h (modified) (1 diff)
• iprt/x86.h (modified) (3 diffs)
• iprt/x86.mac (modified) (1 diff)

trunk/include/VBox/vmm/dbgf.h

@@ -1278 +1278 @@
     uint64_t    u64;            /**< The 64-bit view. */
     RTUINT128U  u128;           /**< The 128-bit view. */
-    RTFLOAT80U2 r80;            /**< The 80-bit floating point view. */
+    RTFLOAT80U  r80;            /**< The 80-bit floating point view. */
+    RTFLOAT80U2 r80Ex;          /**< The 80-bit floating point view v2. */
     /** GDTR or LDTR (DBGFREGVALTYPE_DTR). */
     struct

trunk/include/iprt/x86.h

@@ -1971 +1971 @@
         X86FPUMMX   fpu;
         /** Extended precision floating point view. */
-        RTFLOAT80U2 r80;
+        RTFLOAT80U  r80;
+        /** Extended precision floating point view v2. */
+        RTFLOAT80U2 r80Ex;
         /** 8-bit view. */
         uint8_t     au8[16];
@@ -2027 +2029 @@
         X86FPUMMX   fpu;
         /** Extended precision floating point view. */
-        RTFLOAT80U2 r80;
+        RTFLOAT80U  r80;
+        /** Extended precision floating point view v2 */
+        RTFLOAT80U2 r80Ex;
         /** 8-bit view. */
         uint8_t     au8[16];
@@ -2117 +2121 @@
 /** Exception Mask: Precision.  */
 #define X86_FCW_PM          RT_BIT(5)
+/** Mask all exceptions.  */
+#define X86_FCW_MASK_ALL    UINT16_C(0x007f)
 /** Precision control mask. */
 #define X86_FCW_PC_MASK     UINT16_C(0x0300)

trunk/include/iprt/x86.mac

@@ -480 +480 @@
 %define X86_FCW_UM          RT_BIT(4)
 %define X86_FCW_PM          RT_BIT(5)
+%define X86_FCW_MASK_ALL    0x007f
 %define X86_FCW_PC_MASK     0x0300
 %define X86_FCW_PC_24       0x0000