Changeset 40138 in vbox for trunk/src

Timestamp:

Feb 15, 2012 4:40:03 PM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

76289

Message:

IEM: fdiv work. Added x86extra.mac for non-automatic x86.h bits.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl.asm (modified) (1 diff)
• testcase/tstX86-1.cpp (modified) (4 diffs)
• testcase/tstX86-1A.asm (modified) (63 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -1278 +1278 @@
 
 
-;;
-; The state saved by FXSAVE.
-; @todo move to x86.mac.
-;
-struc X86FXSTATE
-    .FCW            resw 1
-    .FSW            resw 1
-    .FTW            resw 1
-    .FOP            resw 1
-    .FPUIP          resd 1
-    .CS             resw 1
-    .Rsrvd1         resw 1
-    .FPUDP          resd 1
-    .DS             resw 1
-    .Rsrvd2         resw 1
-    .MXCSR          resd 1
-    .MXCSR_MASK     resd 1
-    .r0             resd 4
-    .r1             resd 4
-    .r2             resd 4
-    .r3             resd 4
-    .r4             resd 4
-    .r5             resd 4
-    .r6             resd 4
-    .r7             resd 4
-    .xmm0           resd 4
-    .xmm1           resd 4
-    .xmm2           resd 4
-    .xmm3           resd 4
-    .xmm4           resd 4
-    .xmm5           resd 4
-    .xmm6           resd 4
-    .xmm7           resd 4
-    .xmm8           resd 4
-    .xmm9           resd 4
-    .xmm10          resd 4
-    .xmm11          resd 4
-    .xmm12          resd 4
-    .xmm13          resd 4
-    .xmm14          resd 4
-    .xmm15          resd 4
-    .au32RsrvdRest  resd 24
-endstruc
-
 %macro FPU_SAFE_INIT 1
         fninit

trunk/src/VBox/VMM/testcase/tstX86-1.cpp

@@ -72 +72 @@
 DECLASM(int32_t) x861_Test5(void);
 DECLASM(int32_t) x861_Test6(void);
+DECLASM(int32_t) x861_TestFPUInstr1(void);
 
 
@@ -179 +180 @@
 
 
+
 int main()
 {
@@ -239 +241 @@
         if (rc != 0)
             RTTestFailed(hTest, "x861_Test4 -> %d", rc);
-#endif
 
         RTTestSub(hTest, "Odd floating point encodings");
@@ -250 +251 @@
         if (rc != 0)
             RTTestFailed(hTest, "x861_Test6 -> %d", rc);
+#endif
+
+        rc = x861_TestFPUInstr1();
+        if (rc != 0)
+            RTTestFailed(hTest, "x861_TestFPUInstr1 -> %d", rc);
     }
 

trunk/src/VBox/VMM/testcase/tstX86-1A.asm

@@ -33 +33 @@
 
 
+%ifdef RT_ARCH_AMD64
+ %define arch_fxsave    o64 fxsave
+ %define arch_fxrstor   o64 fxrstor
+%else
+ %define arch_fxsave    fxsave
+ %define arch_fxrstor   fxrstor
+%endif
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;   Global Variables                                                          ;
@@ -45 +53 @@
 %define g_cchAlpha (g_szAlpha_end - NAME(g_szAlpha))
         db      0, 0, 0,
+
+;; @name Floating point constants.
+; @{
+g_r32_0dot1:    dd 0.1
+g_r32_3dot2:    dd 3.2
+g_r32_Zero:     dd 0.0
+g_r32_One:      dd 1.0
+g_r32_Two:      dd 2.0
+g_r32_Three:    dd 3.0
+g_r32_Ten:      dd 10.0
+g_r32_Eleven:   dd 11.0
+g_r32_ThirtyTwo:dd 32.0
+g_r32_Min:      dd 000800000h
+g_r32_Max:      dd 07f7fffffh
+g_r32_Inf:      dd 07f800000h
+g_r32_SNaN:     dd 07f800001h
+g_r32_SNaNMax:  dd 07fbfffffh
+g_r32_QNaN:     dd 07fc00000h
+g_r32_QNaNMax:  dd 07fffffffh
+
+g_r64_0dot1:    dq 0.1
+g_r64_6dot9:    dq 6.9
+g_r64_Zero:     dq 0.0
+g_r64_One:      dq 1.0
+g_r64_Two:      dq 2.0
+g_r64_Three:    dq 3.0
+g_r64_Ten:      dq 10.0
+g_r64_Eleven:   dq 11.0
+g_r64_ThirtyTwo:dq 32.0
+g_r64_Min:      dq 00010000000000000h
+g_r64_Max:      dq 07fefffffffffffffh
+g_r64_Inf:      dq 07ff0000000000000h
+g_r64_SNaN:     dq 07ff0000000000001h
+g_r64_SNaNMax:  dq 07ff7ffffffffffffh
+g_r64_QNaN:     dq 07ff8000000000000h
+g_r64_QNaNMax:  dq 07fffffffffffffffh
+g_r64_DnMin:    dq 00000000000000001h
+g_r64_DnMax:    dq 0000fffffffffffffh
+
+
+g_r80_0dot1:    dt 0.1
+g_r80_3dot2:    dt 3.2
+g_r80_Zero:     dt 0.0
+g_r80_One:      dt 1.0
+g_r80_Two:      dt 2.0
+g_r80_Three:    dt 3.0
+g_r80_Ten:      dt 10.0
+g_r80_Eleven:   dt 11.0
+g_r80_ThirtyTwo:dt 32.0
+g_r80_Min:      dt 000018000000000000000h
+g_r80_Max:      dt 07ffeffffffffffffffffh
+g_r80_Inf:      dt 07fff8000000000000000h
+
+g_r32V1:        dd 3.2
+g_r32V2:        dd -1.9
+g_r64V1:        dq 6.4
+g_r80V1:        dt 8.0
+
+; Denormal numbers.
+g_r32D0:        dd 000200000h
+;; @}
+
+;; @name Upconverted Floating point constants
+; @{
+;g_r80_r32_0dot1:        dt 0.1
+g_r80_r32_3dot2:        dt 04000cccccd0000000000h
+;g_r80_r32_Zero:         dt 0.0
+;g_r80_r32_One:          dt 1.0
+;g_r80_r32_Two:          dt 2.0
+;g_r80_r32_Three:        dt 3.0
+;g_r80_r32_Ten:          dt 10.0
+;g_r80_r32_Eleven:       dt 11.0
+;g_r80_r32_ThirtyTwo:    dt 32.0
+;; @}
+
+;; @name Decimal constants.
+; @{
+g_u64Zero:      dd 0
+g_u32Zero:      dw 0
+g_u64Two:       dd 2
+g_u32Two:       dw 2
+;; @}
+
 
 ;;
@@ -63 +154 @@
 ;; Reference a variable
 %ifdef RT_ARCH_AMD64
- %define REF(a_Name)     [a_Name wrt rip]
+ %define REF(a_Name)     a_Name wrt rip
 %else
- %define REF(a_Name)     [a_Name]
+ %define REF(a_Name)     a_Name
 %endif
 
 ;; Reference a global variable
 %ifdef RT_ARCH_AMD64
- %define REF_GLOBAL(a_Name)     [NAME(a_Name) wrt rip]
+ %define REF_EXTERN(a_Name)     NAME(a_Name) wrt rip
 %else
- %define REF_GLOBAL(a_Name)     [NAME(a_Name)]
+ %define REF_EXTERN(a_Name)     NAME(a_Name)
 %endif
 
@@ -125 +216 @@
 BEGINCODE
 %%resume:
-        FpuCheckFSW ((%1) | X86_FSW_B | X86_FSW_ES), %2
+        FpuCheckFSW ((%1) | X86_FSW_ES | X86_FSW_B), %2
         fnclex
 %endmacro
 
 ;;
-; Macro for recording a FPU instruction trapping on a following fwait.
+; Macro for recording checking the FSW value.
 ;
 ; Uses stack.
@@ -148 +239 @@
         jmp     .return
 %%ok:
-        fnstsw  ax
 %endmacro
 
@@ -172 +262 @@
 %endmacro
 
-
-;;
-; Function prologue saving all registers except EAX.
+;; Checks that ST0 contains QNaN.
+%define CheckSt0Value_QNaN              CheckSt0Value 0x00000000, 0xc0000000, 0xffff
+;; Checks that ST0 contains +Inf.
+%define CheckSt0Value_PlusInf           CheckSt0Value 0x00000000, 0x80000000, 0x7fff
+;; Checks that ST0 contains 3 & 1/3.
+%define CheckSt0Value_3_and_a_3rd       CheckSt0Value 0x55555555, 0xd5555555, 0x4000
+;; Checks that ST0 contains 3 & 1/3.
+%define CheckSt0Value_3_and_two_3rds    CheckSt0Value 0xaaaaaaab, 0xeaaaaaaa, 0x4000
+
+
+;;
+; Macro for recording checking the FSW value of a FXSAVE image.
+;
+; Uses stack.
+;
+; @param        1       Address expression for the FXSAVE image.
+; @param        2       The status flags that are expected to be set afterwards.
+; @param        3       C0..C3 to mask out in case undefined.
+; @uses         eax
+; @sa   FpuCheckFSW
+;
+%macro FxSaveCheckFSW 3
+%%resume:
+        movzx   eax, word [%1 + X86FXSTATE.FSW]
+        and     eax, ~X86_FSW_TOP_MASK & ~(%3)
+        cmp     eax, (%2)
+        je      %%ok
+        mov     eax, 10000000 + __LINE__
+        jmp     .return
+%%ok:
+%endmacro
+
+
+;;
+; Checks that ST0 is empty in an FXSAVE image.
+;
+; @uses         eax
+; @param        1       Address expression for the FXSAVE image.
+;
+%macro FxSaveCheckSt0Empty 1
+        movzx   eax, word [%1 + X86FXSTATE.FSW]
+        and     eax, X86_FSW_TOP_MASK
+        shr     eax, X86_FSW_TOP_SHIFT
+        bt      [%1 + X86FXSTATE.FTW], eax
+        jnc     %%ok
+        mov     eax, 20000000 + __LINE__
+        jmp     .return
+%%ok:
+%endmacro
+
+
+;;
+; Checks that ST0 is not-empty in an FXSAVE image.
+;
+; @uses         eax
+; @param        1       Address expression for the FXSAVE image.
+;
+%macro FxSaveCheckSt0NonEmpty 1
+        movzx   eax, word [%1 + X86FXSTATE.FSW]
+        and     eax, X86_FSW_TOP_MASK
+        shr     eax, X86_FSW_TOP_SHIFT
+        bt      [%1 + X86FXSTATE.FTW], eax
+        jc      %%ok
+        mov     eax, 30000000 + __LINE__
+        jmp     .return
+%%ok:
+%endmacro
+
+;;
+; Checks that ST0 in a FXSAVE image has a certain value (empty or not
+; is ignored).
+;
+; @uses         eax
+; @param        1       Address expression for the FXSAVE image.
+; @param        2       First dword of value.
+; @param        3       Second dword of value.
+; @param        4       Final word of value.
+;
+%macro FxSaveCheckSt0ValueEx 4
+        cmp     dword [%1 + X86FXSTATE.st0], %2
+        je      %%ok1
+%%bad:
+        mov     eax, 40000000 + __LINE__
+        jmp     .return
+%%ok1:
+        cmp     dword [%1 + X86FXSTATE.st0 + 4], %3
+        jne     %%bad
+        cmp     word  [%1 + X86FXSTATE.st0 + 8], %4
+        jne     %%bad
+%endmacro
+
+
+;;
+; Checks if ST0 in a FXSAVE image has the same value as the specified
+; floating point (80-bit) constant.
+;
+; @uses         eax, xDX
+; @param        1       Address expression for the FXSAVE image.
+; @param        2       The address expression of the constant.
+;
+%macro FxSaveCheckSt0ValueConstEx 2
+        mov     eax, [%2]
+        cmp     dword [%1 + X86FXSTATE.st0], eax
+        je      %%ok1
+%%bad:
+        mov     eax, 40000000 + __LINE__
+        jmp     .return
+%%ok1:
+        mov     eax, [4 + %2]
+        cmp     dword [%1 + X86FXSTATE.st0 + 4], eax
+        jne     %%bad
+        mov     ax, [8 + %2]
+        cmp     word  [%1 + X86FXSTATE.st0 + 8], ax
+        jne     %%bad
+%endmacro
+
+
+;;
+; Checks that ST0 in a FXSAVE image has a certain value.
+;
+; @uses         eax
+; @param        1       Address expression for the FXSAVE image.
+; @param        2       First dword of value.
+; @param        3       Second dword of value.
+; @param        4       Final word of value.
+;
+%macro FxSaveCheckSt0Value 4
+        FxSaveCheckSt0NonEmpty %1
+        FxSaveCheckSt0ValueEx %1, %2, %3, %4
+%endmacro
+
+
+;;
+; Checks that ST0 in a FXSAVE image is empty and that the value stored is the
+; init value set by FpuInitWithCW.
+;
+; @uses         eax
+; @param        1       Address expression for the FXSAVE image.
+;
+%macro FxSaveCheckSt0EmptyInitValue 1
+        FxSaveCheckSt0Empty %1
+        FxSaveCheckSt0ValueEx %1, 0x40404040, 0x40404040, 0xffff
+%endmacro
+
+;;
+; Checks that ST0 in a FXSAVE image is non-empty and has the same value as the
+; specified constant (80-bit).
+;
+; @uses         eax, xDX
+; @param        1       Address expression for the FXSAVE image.
+; @param        2       The address expression of the constant.
+%macro FxSaveCheckSt0ValueConst 2
+        FxSaveCheckSt0NonEmpty %1
+        FxSaveCheckSt0ValueConstEx %1, %2
+%endmacro
+
+;; Checks that ST0 contains QNaN.
+%define FxSaveCheckSt0Value_QNaN(p)              FxSaveCheckSt0Value p, 0x00000000, 0xc0000000, 0xffff
+;; Checks that ST0 contains +Inf.
+%define FxSaveCheckSt0Value_PlusInf(p)           FxSaveCheckSt0Value p, 0x00000000, 0x80000000, 0x7fff
+;; Checks that ST0 contains 3 & 1/3.
+%define FxSaveCheckSt0Value_3_and_a_3rd(p)       FxSaveCheckSt0Value p, 0x55555555, 0xd5555555, 0x4000
+;; Checks that ST0 contains 3 & 1/3.
+%define FxSaveCheckSt0Value_3_and_two_3rds(p)    FxSaveCheckSt0Value p, 0xaaaaaaab, 0xeaaaaaaa, 0x4000
+
+
+;;
+; Function prologue saving all registers except EAX and aligns the stack
+; on a 16-byte boundrary.
 ;
 %macro SAVE_ALL_PROLOGUE 0
@@ -195 +451 @@
         push    r15
 %endif
+        and     xSP, ~0fh;
 %endmacro
 
@@ -203 +460 @@
 %macro SAVE_ALL_EPILOGUE 0
 %ifdef RT_ARCH_AMD64
+        lea     rsp, [rbp - 14 * 8]
         pop     r15
         pop     r14
@@ -211 +469 @@
         pop     r9
         pop     r8
+%else
+        lea     esp, [ebp - 6 * 4]
 %endif
         pop     xDI
@@ -285 +545 @@
 ;
 x861_LoadUniqueRegValuesSSE:
-        movq    mm0, REF(._mm0)
-        movq    mm1, REF(._mm1)
-        movq    mm2, REF(._mm2)
-        movq    mm3, REF(._mm3)
-        movq    mm4, REF(._mm4)
-        movq    mm5, REF(._mm5)
-        movq    mm6, REF(._mm6)
-        movq    mm7, REF(._mm7)
-        movdqu  xmm0, REF(._xmm0)
-        movdqu  xmm1, REF(._xmm1)
-        movdqu  xmm2, REF(._xmm2)
-        movdqu  xmm3, REF(._xmm3)
-        movdqu  xmm4, REF(._xmm4)
-        movdqu  xmm5, REF(._xmm5)
-        movdqu  xmm6, REF(._xmm6)
-        movdqu  xmm7, REF(._xmm7)
+        fninit
+        movq    mm0, [REF(._mm0)]
+        movq    mm1, [REF(._mm1)]
+        movq    mm2, [REF(._mm2)]
+        movq    mm3, [REF(._mm3)]
+        movq    mm4, [REF(._mm4)]
+        movq    mm5, [REF(._mm5)]
+        movq    mm6, [REF(._mm6)]
+        movq    mm7, [REF(._mm7)]
+        movdqu  xmm0, [REF(._xmm0)]
+        movdqu  xmm1, [REF(._xmm1)]
+        movdqu  xmm2, [REF(._xmm2)]
+        movdqu  xmm3, [REF(._xmm3)]
+        movdqu  xmm4, [REF(._xmm4)]
+        movdqu  xmm5, [REF(._xmm5)]
+        movdqu  xmm6, [REF(._xmm6)]
+        movdqu  xmm7, [REF(._xmm7)]
 %ifdef RT_ARCH_AMD64
-        movdqu  xmm8,  REF(._xmm8)
-        movdqu  xmm9,  REF(._xmm9)
-        movdqu  xmm10, REF(._xmm10)
-        movdqu  xmm11, REF(._xmm11)
-        movdqu  xmm12, REF(._xmm12)
-        movdqu  xmm13, REF(._xmm13)
-        movdqu  xmm14, REF(._xmm14)
-        movdqu  xmm15, REF(._xmm15)
+        movdqu  xmm8,  [REF(._xmm8)]
+        movdqu  xmm9,  [REF(._xmm9)]
+        movdqu  xmm10, [REF(._xmm10)]
+        movdqu  xmm11, [REF(._xmm11)]
+        movdqu  xmm12, [REF(._xmm12)]
+        movdqu  xmm13, [REF(._xmm13)]
+        movdqu  xmm14, [REF(._xmm14)]
+        movdqu  xmm15, [REF(._xmm15)]
 %endif
         call    x861_LoadUniqueRegValues
@@ -343 +604 @@
 
 ;;
-; Clears all general, MMX and SSE registers except xBP and xSP.
+; Clears all MMX and SSE registers.
 ;
 x861_ClearRegistersSSE:
-        call    x861_ClearRegisters
-        movq    mm0,   REF(.zero)
-        movq    mm1,   REF(.zero)
-        movq    mm2,   REF(.zero)
-        movq    mm3,   REF(.zero)
-        movq    mm4,   REF(.zero)
-        movq    mm5,   REF(.zero)
-        movq    mm6,   REF(.zero)
-        movq    mm7,   REF(.zero)
-        movdqu  xmm0,  REF(.zero)
-        movdqu  xmm1,  REF(.zero)
-        movdqu  xmm2,  REF(.zero)
-        movdqu  xmm3,  REF(.zero)
-        movdqu  xmm4,  REF(.zero)
-        movdqu  xmm5,  REF(.zero)
-        movdqu  xmm6,  REF(.zero)
-        movdqu  xmm7,  REF(.zero)
+        fninit
+        movq    mm0,   [REF(.zero)]
+        movq    mm1,   [REF(.zero)]
+        movq    mm2,   [REF(.zero)]
+        movq    mm3,   [REF(.zero)]
+        movq    mm4,   [REF(.zero)]
+        movq    mm5,   [REF(.zero)]
+        movq    mm6,   [REF(.zero)]
+        movq    mm7,   [REF(.zero)]
+        movdqu  xmm0,  [REF(.zero)]
+        movdqu  xmm1,  [REF(.zero)]
+        movdqu  xmm2,  [REF(.zero)]
+        movdqu  xmm3,  [REF(.zero)]
+        movdqu  xmm4,  [REF(.zero)]
+        movdqu  xmm5,  [REF(.zero)]
+        movdqu  xmm6,  [REF(.zero)]
+        movdqu  xmm7,  [REF(.zero)]
 %ifdef RT_ARCH_AMD64
-        movdqu  xmm8,  REF(.zero)
-        movdqu  xmm9,  REF(.zero)
-        movdqu  xmm10, REF(.zero)
-        movdqu  xmm11, REF(.zero)
-        movdqu  xmm12, REF(.zero)
-        movdqu  xmm13, REF(.zero)
-        movdqu  xmm14, REF(.zero)
-        movdqu  xmm15, REF(.zero)
+        movdqu  xmm8,  [REF(.zero)]
+        movdqu  xmm9,  [REF(.zero)]
+        movdqu  xmm10, [REF(.zero)]
+        movdqu  xmm11, [REF(.zero)]
+        movdqu  xmm12, [REF(.zero)]
+        movdqu  xmm13, [REF(.zero)]
+        movdqu  xmm14, [REF(.zero)]
+        movdqu  xmm15, [REF(.zero)]
 %endif
-        call    x861_LoadUniqueRegValues
         ret
 
@@ -380 +640 @@
 ; x861_ClearRegistersSSE
 
+
+;;
+; Loads all general, MMX and SSE registers except xBP and xSP with unique values.
+;
+x861_LoadUniqueRegValuesSSEAndGRegs:
+        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValues
+        ret
+
+;;
+; Clears all general, MMX and SSE registers except xBP and xSP.
+;
+x861_ClearRegistersSSEAndGRegs:
+        call    x861_ClearRegistersSSE
+        call    x861_ClearRegisters
+        ret
 
 BEGINPROC x861_Test1
@@ -544 +820 @@
         ; Loading is always a word access.
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         lea     xDI, [xDI + 0x1000 - 2]
         mov     xDX, es
@@ -552 +828 @@
         ; Saving is always a word access.
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         mov     dword [xDI + 0x1000 - 4], -1
         mov     [xDI + 0x1000 - 2], ss ; Should not crash.
@@ -564 +840 @@
         call    x861_ClearRegisters
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         mov     dword [xDI + 0x1000 - 4], -1
         db 04ah
@@ -583 +859 @@
 
         ; check that repne scasb (al=0) behaves like expected.
-        lea     xDI, REF_GLOBAL(g_szAlpha)
+        lea     xDI, [REF(g_szAlpha)]
         xor     eax, eax                ; find the end
         mov     ecx, g_cchAlpha + 1
@@ -592 +868 @@
 
         ; check that repe scasb (al=0) behaves like expected.
-        lea     xDI, REF_GLOBAL(g_szAlpha)
+        lea     xDI, [REF(g_szAlpha)]
         xor     eax, eax                ; find the end
         mov     ecx, g_cchAlpha + 1
@@ -601 +877 @@
 
         ; repne is last, it wins.
-        lea     xDI, REF_GLOBAL(g_szAlpha)
+        lea     xDI, [REF(g_szAlpha)]
         xor     eax, eax                ; find the end
         mov     ecx, g_cchAlpha + 1
@@ -612 +888 @@
 
         ; repe is last, it wins.
-        lea     xDI, REF_GLOBAL(g_szAlpha)
+        lea     xDI, [REF(g_szAlpha)]
         xor     eax, eax                ; find the end
         mov     ecx, g_cchAlpha + 1
@@ -628 +904 @@
         mov     dx, ds
         mov     es, dx
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         xor     eax, eax
         mov     ecx, 01000h
         rep stosb
 
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         mov     ecx, 4
         mov     eax, 0ffh
@@ -642 +918 @@
         jne     .failed
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         cmp     dword [xDI], 0ffffffffh
         jne     .failed
@@ -648 +924 @@
         jne     .failed
 
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         mov     ecx, 4
         mov     eax, 0feh
@@ -657 +933 @@
         jne     .failed
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         cmp     dword [xDI], 0fefefefeh
         jne     .failed
@@ -670 +946 @@
         mov     dx, ds
         mov     es, dx
-        mov     xDI, REF_GLOBAL(g_pbEfPage)
+        mov     xDI, [REF_EXTERN(g_pbEfPage)]
         xor     xCX, xCX
         rep stosb                       ; no trap
@@ -702 +978 @@
         ;
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 8h
         mov     byte [xDI+0], 0f0h
@@ -712 +988 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 7h
         mov     byte [xDI+0], 0f0h
@@ -721 +997 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 4h
         mov     byte [xDI+0], 0f0h
@@ -730 +1006 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 6h
         mov     byte [xDI+0], 0f0h
@@ -741 +1017 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 5h
         mov     byte [xDI+0], 0f0h
@@ -751 +1027 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 4h
         mov     byte [xDI+0], 0f0h
@@ -760 +1036 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 3h
         mov     byte [xDI+0], 0f0h
@@ -768 +1044 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 2h
         mov     byte [xDI+0], 0f0h
@@ -775 +1051 @@
 
         mov     eax, __LINE__
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, 1000h - 1h
         mov     byte [xDI+0], 0f0h
@@ -819 +1095 @@
 
         ; Check testcase preconditions.
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db       00Fh, 073h, 0D0h, 080h  ;    psrlq   mm0, 128
         call    .check_mm0_zero_and_xmm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 00Fh, 073h, 0D0h, 080h  ;    psrlq   xmm0, 128
@@ -836 +1112 @@
 
         ; General checks that order does not matter, etc.
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 026h, 066h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 026h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 067h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 067h, 066h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 067h, 066h, 065h, 00Fh, 073h, 0D0h, 080h
@@ -862 +1138 @@
 
 %ifdef RT_ARCH_AMD64
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 048h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.W
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 044h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.R
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 042h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.X
@@ -878 +1154 @@
 
         ; Actually for REX, order does matter if the prefix is used.
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 041h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.B
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 041h, 00Fh, 073h, 0D0h, 080h ; REX.B
@@ -890 +1166 @@
 
         ; Check all ignored prefixes (repeates some of the above).
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 026h, 00Fh, 073h, 0D0h, 080h ; es
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 065h, 00Fh, 073h, 0D0h, 080h ; gs
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 064h, 00Fh, 073h, 0D0h, 080h ; fs
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 02eh, 00Fh, 073h, 0D0h, 080h ; cs
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 036h, 00Fh, 073h, 0D0h, 080h ; ss
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 03eh, 00Fh, 073h, 0D0h, 080h ; ds
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 067h, 00Fh, 073h, 0D0h, 080h ; addr size
@@ -926 +1202 @@
 
 %ifdef RT_ARCH_AMD64
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 048h, 00Fh, 073h, 0D0h, 080h ; REX.W
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 044h, 00Fh, 073h, 0D0h, 080h ; REX.R
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 042h, 00Fh, 073h, 0D0h, 080h ; REX.X
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 041h, 00Fh, 073h, 0D0h, 080h ; REX.B - has actual effect on the instruction.
@@ -948 +1224 @@
 
         ; Repeated prefix until we hit the max opcode limit.
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 066h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 066h, 066h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 00Fh, 073h, 0D0h, 080h
@@ -972 +1248 @@
 %ifdef RT_ARCH_AMD64
         ; Repeated REX is parsed, but only the last byte matters.
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 041h, 048h, 00Fh, 073h, 0D0h, 080h ; REX.B, REX.W
         call    .check_xmm0_zero_and_mm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 048h, 041h, 00Fh, 073h, 0D0h, 080h ; REX.B, REX.W
         call    .check_xmm8_zero_and_xmm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 048h, 044h, 042h, 048h, 044h, 042h, 048h, 044h, 042h, 041h, 00Fh, 073h, 0D0h, 080h
         call    .check_xmm8_zero_and_xmm0_nz
 
-        call    x861_LoadUniqueRegValuesSSE
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
         mov     eax, __LINE__
         db 066h, 041h, 041h, 041h, 041h, 041h, 041h, 041h, 041h, 041h, 04eh, 00Fh, 073h, 0D0h, 080h
@@ -1093 +1369 @@
 BEGINPROC   x861_Test3
         SAVE_ALL_PROLOGUE
-        call    x861_LoadUniqueRegValuesSSE
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
 
         ; Check testcase preconditions.
-        fxsave  [xDI]
-        fxrstor [xDI]
+        fxsave   [xDI]
+        fxrstor  [xDI]
 
         add     xDI, PAGE_SIZE - 512
@@ -1126 +1402 @@
 
         ; Check that a save + restore + save cycle yield the same results.
-        mov     xBX, REF_GLOBAL(g_pbEfExecPage)
+        mov     xBX, [REF_EXTERN(g_pbEfExecPage)]
         mov     xDI, xBX
         mov     eax, 066778899h
@@ -1134 +1410 @@
         fxsave  [xBX]
 
-        call    x861_ClearRegistersSSE
-        mov     xBX, REF_GLOBAL(g_pbEfExecPage)
+        call    x861_ClearRegistersSSEAndGRegs
+        mov     xBX, [REF_EXTERN(g_pbEfExecPage)]
         fxrstor [xBX]
 
@@ -1150 +1426 @@
         ; 464:511 are available to software use.  Let see how carefully access
         ; to the full 512 bytes are checked...
-        call    x861_LoadUniqueRegValuesSSE
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, PAGE_SIZE - 512
         ShouldTrap X86_XCPT_PF, fxsave  [xDI + 16]
@@ -1227 +1503 @@
         mov     ebx, 16
 .fxsave_pf_effect_loop:
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, PAGE_SIZE - 512 * 2
         mov     xSI, xDI
@@ -1249 +1525 @@
 
         ; Lets check that a FP in fxrstor does not have any effect on the FPU or SSE state.
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         mov     ecx, PAGE_SIZE / 4
         mov     eax, 0ffaa33cch
@@ -1255 +1531 @@
         rep stosd
 
-        call    x861_LoadUniqueRegValuesSSE
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        call    x861_LoadUniqueRegValuesSSEAndGRegs
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         fxsave  [xDI]
 
-        call    x861_ClearRegistersSSE
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        call    x861_ClearRegistersSSEAndGRegs
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         fxsave  [xDI + 512]
 
         mov     ebx, 16
 .fxrstor_pf_effect_loop:
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         mov     xSI, xDI
         lea     xDI, [xDI + PAGE_SIZE - 512 + xBX]
@@ -1274 +1550 @@
 
         push    xBX
-        call    x861_ClearRegistersSSE
+        call    x861_ClearRegistersSSEAndGRegs
         pop     xBX
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         ShouldTrap X86_XCPT_PF, fxrstor  [xDI + PAGE_SIZE - 512 + xBX] ; try load unique state
 
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         lea     xSI, [xDI + 512]        ; point it to the clean state, which is what we expect.
         lea     xDI, [xDI + 1024]
@@ -1389 +1665 @@
         sub     xSP, 2048
         and     xSP, ~0fh
-        fxsave  [xSP + 1024]
+        arch_fxsave [xSP + 1024]
         %1
         call    SaveFPUAndGRegsToStack
 
-        fxrstor [xSP + 1024]
+        arch_fxrstor [xSP + 1024]
         %2
         call    CompareFPUAndGRegsOnStack
-        ;fxrstor [xSP + 1024]
+        ;arch_fxrstor [xSP + 1024]
         leave
 
@@ -1433 +1709 @@
 
         ; Save the FPU state.
-        fxsave  [xSP + xS]
+        arch_fxsave [xSP + xS]
 
         ; Save GRegs (80h bytes).
@@ -1515 +1791 @@
         lea     xDI, [xSI + 1024]
 
-        mov     dword [xSI + 0x8], 0    ; ignore FPUIP
-        mov     dword [xDI + 0x8], 0    ; ignore FPUIP
+        mov     word [xSI + X86FXSTATE.FOP], 0          ; ignore
+        mov     dword [xSI + X86FXSTATE.FPUIP], 0       ; ignore
+        mov     dword [xDI + X86FXSTATE.FPUDP], 0       ; ignore
 
         cld
@@ -1522 +1799 @@
         je      .ok
 
-        int3
+        ;int3
         lea     xAX, [xSP + xS*3]
         xchg    xAX, xSI
@@ -1559 +1836 @@
 
         ; standard stuff...
-        fld dword REF(.r32V1)
-        fld qword REF(.r64V1)
-        fld tword REF(.r80V1)
-        fld qword REF(.r64V1)
-        fld dword REF(.r32V2)
-        fld dword REF(.r32V1)
+        fld dword [REF(g_r32V1)]
+        fld qword [REF(g_r64V1)]
+        fld tword [REF(g_r80V1)]
+        fld qword [REF(g_r64V1)]
+        fld dword [REF(g_r32V2)]
+        fld dword [REF(g_r32V1)]
 
         ; Test the nop check.
@@ -1767 +2044 @@
         ret
 
-.r32V1: dd 3.2
-.r32V2: dd -1.9
-.r64V1: dq 6.4
-.r80V1: dt 8.0
-
-; Denormal numbers.
-.r32D0: dd 0200000h
-
 ENDPROC     x861_Test5
 
@@ -1788 +2057 @@
 
         ; Load some pointers.
-        lea     xSI, REF(.r32V1)
-        mov     xDI, REF_GLOBAL(g_pbEfExecPage)
+        lea     xSI, [REF(g_r32V1)]
+        mov     xDI, [REF_EXTERN(g_pbEfExecPage)]
         add     xDI, PAGE_SIZE          ; invalid page.
 
@@ -1799 +2068 @@
         mov     dword [xSP], X86_FCW_PC_64 | X86_FCW_RC_NEAREST
         fldcw   [xSP]
-        FpuShouldTrap  X86_FSW_DE, 0, fld dword REF(.r32D0)
+        FpuShouldTrap  X86_FSW_DE, 0, fld dword [REF(g_r32D0)]
         CheckSt0Value 0x00000000, 0x80000000, 0x3f7f
 
         mov     dword [xSP], X86_FCW_PC_64 | X86_FCW_RC_NEAREST | X86_FCW_DM
         fldcw   [xSP]
-        fld     dword REF(.r32D0)
+        fld     dword [REF(g_r32D0)]
         fwait
         FpuCheckFSW X86_FSW_DE, 0
@@ -1815 +2084 @@
         mov     dword [xSP], X86_FCW_PC_64 | X86_FCW_RC_NEAREST
         fldcw   [xSP]
-        fld     qword REF(.r64V1)
+        fld     qword [REF(g_r64V1)]
         fld     dword [xSI]
         fld     dword [xSI]
@@ -1822 +2091 @@
         fld     dword [xSI]
         fld     dword [xSI]
-        fld     tword REF(.r80V1)
+        fld     tword [REF(g_r80V1)]
         fwait
 
@@ -1854 +2123 @@
         CheckSt0Value 0x00000000, 0xc0000000, 0xffff
 
-        fld     qword REF(.r64V1)
+        fld     qword [REF(g_r64V1)]
         FpuCheckFSW X86_FSW_IE | X86_FSW_SF | X86_FSW_C1, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
         fnclex
@@ -1860 +2129 @@
 
         ; This is includes denormal values.
-        fld     dword REF(.r32D0)
+        fld     dword [REF(g_r32D0)]
         fwait
         FpuCheckFSW X86_FSW_IE | X86_FSW_SF | X86_FSW_C1, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
@@ -1872 +2141 @@
         mov     dword [xSP], X86_FCW_PC_64 | X86_FCW_RC_NEAREST
         fldcw   [xSP]
-        fld     qword REF(.r64V1)
+        fld     qword [REF(g_r64V1)]
         ShouldTrap X86_XCPT_MF, fld     dword [xDI]
         fnclex
@@ -1900 +2169 @@
         SAVE_ALL_EPILOGUE
         ret
-
-.r32V1: dd 3.2
-.r64V1: dq 6.4
-.r80V1: dt 8.0
-
-; Denormal numbers.
-.r32D0: dd 0200000h
-
 ENDPROC     x861_Test6
+
+
+extern NAME(RTTestISub)
+
+;;
+; Sets the current subtest.
+%macro SetSubTest 1
+%ifdef RT_ARCH_AMD64
+ %ifdef ASM_CALL64_GCC
+        lea     rdi, [%%s_szName wrt rip]
+ %else
+        lea     rcx, [%%s_szName wrt rip]
+ %endif
+        call    NAME(RTTestISub)
+%else
+        push    %%s_szName
+        call    NAME(RTTestISub)
+        add     esp, 4
+%endif
+        jmp     %%done
+%%s_szName:
+        db %1, 0
+%%done:
+%endmacro
+
+
+;;
+; Checks the opcode and CS:IP FPU.
+;
+; @returns ZF=1 on success, ZF=0 on failure.
+; @param    xSP + xS    fxsave image followed by fnstenv.
+; @param    xCX         Opcode address (no prefixes).
+;
+CheckOpcodeCsIp:
+        push    xBP
+        mov     xBP, xSP
+        push    xAX
+
+        ; Check the IP.
+%ifdef RT_ARCH_AMD64
+        cmp     rcx, [xBP + xS*2 + X86FXSTATE.FPUIP]
+%else
+        cmp     ecx, [xBP + xS*2 + X86FXSTATE.FPUIP]
+%endif
+        jne     .failure1
+
+        mov     ax, cs
+        cmp     ax, [xBP + xS*2 + 512 + X86FSTENV32P.FPUCS]
+        jne     .failure2
+
+        ; Check the opcode.  This may be disabled.
+        cmp     word [xBP + xS*2 + X86FXSTATE.FOP], 0
+        je      .success
+
+        mov     ah, [xCX]
+        mov     al, [xCX + 1]
+        and     ax, 07ffh
+        cmp     ax, [xBP + xS*2 + X86FXSTATE.FOP]
+        jne     .failure3
+
+.success:
+        xor     eax, eax                ; clear Z
+.return:
+        pop     xAX
+        leave
+        ret
+
+.failure1:
+        mov     eax, 10000000
+        jmp     .failure
+.failure2:
+        mov     eax, 20000000
+        jmp     .failure
+.failure3:
+        mov     eax, 30000000
+        jmp     .failure
+.failure:
+        or      eax, eax
+        leave
+        ret
+
+
+
+
+
+;;
+; Checks the opcode, CS:IP and DS:DP of the FPU.
+;
+; @returns ZF=1 on success, ZF=0+EAX on failure.
+; @param    xSP + xS    fxsave image followed by fnstenv.
+; @param    xCX         Opcode address (no prefixes).
+; @param    xDX         Memory address (DS relative).
+;
+CheckOpcodeCsIpDsDp:
+        push    xBP
+        mov     xBP, xSP
+        push    xAX
+
+        ; Check the memory operand.
+%ifdef RT_ARCH_AMD64
+        cmp     rdx, [xBP + xS*2 + X86FXSTATE.FPUDP]
+%else
+        cmp     edx, [xBP + xS*2 + X86FXSTATE.FPUDP]
+%endif
+        jne     .failure1
+
+        mov     ax, ds
+        cmp     ax, [xBP + xS*2 + 512 + X86FSTENV32P.FPUDS]
+        jne     .failure2
+
+.success:
+        pop     xAX
+        leave
+        ; Let CheckOpcodeCsIp to the rest.
+        jmp     CheckOpcodeCsIp
+
+.failure1:
+        mov     eax, 60000000
+        jmp     .failure
+.failure2:
+        mov     eax, 80000000
+.failure:
+        or      eax, eax
+        leave
+        ret
+
+
+;;
+; Checks a FPU instruction taking a memory operand.
+;
+; @uses xCX, xDX, xAX, Stack.
+;
+%macro FpuCheckOpcodeCsIpDsDp 2
+%%instruction:
+        %1
+        arch_fxsave  [xSP]
+        fnstenv [xSP + 512]             ; for the selectors (64-bit)
+        arch_fxrstor [xSP]              ; fnstenv screws up the ES bit.
+        lea     xDX, %2
+        lea     xCX, [REF(%%instruction)]
+        call    CheckOpcodeCsIpDsDp
+        jz      %%ok
+        or      eax, __LINE__
+        jmp     .return
+%%ok:
+%endmacro
+
+
+;;
+; Checks a trapping FPU instruction taking a memory operand.
+;
+; Upon return, there is are two FXSAVE image on the stack at xSP.
+;
+; @uses xCX, xDX, xAX, Stack.
+;
+; @param    %1  The instruction.
+; @param    %2  Operand memory address (DS relative).
+;
+%macro FpuTrapOpcodeCsIpDsDp 2
+%%instruction:
+        %1
+        fxsave [xSP + 1024 +512]        ; FPUDS and FPUCS for 64-bit hosts.
+                                        ; WEIRD: When saved after FWAIT they are ZEROed! (64-bit Intel)
+%%trap:
+        fwait
+%%trap_end:
+        mov     eax, __LINE__
+        jmp     .return
+BEGINDATA
+%%trapinfo: istruc TRAPINFO
+        at TRAPINFO.uTrapPC,    RTCCPTR_DEF     %%trap
+        at TRAPINFO.uResumePC,  RTCCPTR_DEF     %%resume
+        at TRAPINFO.u8TrapNo,   db              X86_XCPT_MF
+        at TRAPINFO.cbInstr,    db              (%%trap_end - %%trap)
+iend
+BEGINCODE
+%%resume:
+        arch_fxsave  [xSP]
+        lea     xDX, %2
+        lea     xCX, [REF(%%instruction)]
+        call    CheckOpcodeCsIpDsDp
+        jz      %%ok
+        or      eax, __LINE__
+        jmp     .return
+%%ok:
+%endmacro
+
+
+;;
+; Initialize the FPU and set CW to %1.
+;
+; @uses dword at [xSP].
+;
+%macro FpuInitWithCW 1
+        call    x861_LoadUniqueRegValuesSSE
+        fninit
+        mov     dword [xSP], %1
+        fldcw   [xSP]
+%endmacro
+
+
+;;
+; First bunch of FPU instruction tests.
+;
+;
+BEGINPROC   x861_TestFPUInstr1
+        SAVE_ALL_PROLOGUE
+        sub     xSP, 2048
+
+        ; Make xBX (preserved accross calls) point to the invalid page.
+        mov     xBX, [REF_EXTERN(g_pbEfExecPage)]
+        add     xBX, PAGE_SIZE
+
+        ;
+        ; FDIV with 64-bit floating point memory operand.
+        ;
+        SetSubTest "FDIV m64r"
+
+        ; ## Normal operation. ##
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld  dword [REF(g_r32_3dot2)]     }, [REF(g_r32_3dot2)]
+        CheckSt0Value 0x00000000, 0xcccccd00, 0x4000
+        FpuCheckOpcodeCsIpDsDp { fdiv qword [REF(g_r64_One)]       }, [REF(g_r64_One)]
+        FpuCheckFSW 0, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value 0x00000000, 0xcccccd00, 0x4000
+
+
+        ; ## Masked exceptions. ##
+        ; Masked stack underflow.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_One)]    }, [REF(g_r64_One)]
+        FpuCheckFSW X86_FSW_IE | X86_FSW_SF, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value_QNaN
+
+        ; Masked zero divide.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_3dot2)]  }, [REF(g_r32_3dot2)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_Zero)]   }, [REF(g_r64_Zero)]
+        FpuCheckFSW X86_FSW_ZE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value_PlusInf
+
+        ; Masked Inf/Inf.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Inf)]    }, [REF(g_r32_Inf)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_Inf)]    }, [REF(g_r64_Inf)]
+        FpuCheckFSW X86_FSW_IE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value_QNaN
+
+        ; Masked 0/0.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Zero)]   }, [REF(g_r32_Zero)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_Zero)]   }, [REF(g_r64_Zero)]
+        FpuCheckFSW X86_FSW_IE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value_QNaN
+
+        ; Masked precision exception, rounded down.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Ten)]    }, [REF(g_r32_Ten)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_Three)]  }, [REF(g_r64_Three)]
+        FpuCheckFSW X86_FSW_PE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value_3_and_a_3rd
+
+        ; Masked precision exception, rounded up.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Eleven)] }, [REF(g_r32_Eleven)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_Three)]  }, [REF(g_r64_Three)]
+        FpuCheckFSW X86_FSW_PE | X86_FSW_C1, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value_3_and_two_3rds
+
+        ; Masked overflow exception.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     tword [REF(g_r80_Max)]    }, [REF(g_r80_Max)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_0dot1)]  }, [REF(g_r64_0dot1)]
+        FpuCheckFSW X86_FSW_PE | X86_FSW_OE | X86_FSW_C1, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value_PlusInf
+
+        ; Masked underflow exception.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     tword [REF(g_r80_Min)]    }, [REF(g_r80_Min)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_Ten)]    }, [REF(g_r64_Ten)]
+        FpuCheckFSW X86_FSW_PE | X86_FSW_UE | X86_FSW_C1, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        CheckSt0Value 0xcccccccd, 0x0ccccccc, 0x0000
+
+        ; Denormal operand.
+        fninit
+        FpuCheckOpcodeCsIpDsDp { fld     tword [REF(g_r80_One)]    }, [REF(g_r80_One)]
+        FpuCheckOpcodeCsIpDsDp { fdiv    qword [REF(g_r64_DnMax)]  }, [REF(g_r64_DnMax)]
+        FxSaveCheckFSW xSP, X86_FSW_DE | X86_FSW_PE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0Value xSP, 0x00000800, 0x80000000, 0x43fd
+
+        ; ## Unmasked exceptions. ##
+%if 1
+        ; Stack underflow - TOP and ST0 unmodified.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_One)]    }, [REF(g_r64_One)]
+        FxSaveCheckFSW xSP, X86_FSW_IE | X86_FSW_SF | X86_FSW_B | X86_FSW_ES, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0EmptyInitValue xSP
+
+        ; Zero divide - Unmodified ST0.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_3dot2)]  }, [REF(g_r32_3dot2)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_Zero)]   }, [REF(g_r64_Zero)]
+        FxSaveCheckFSW xSP, X86_FSW_ZE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0ValueConst xSP, REF(g_r80_r32_3dot2)
+
+        ; Invalid Operand (Inf/Inf) - Unmodified ST0.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Inf)]    }, [REF(g_r32_Inf)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_Inf)]    }, [REF(g_r64_Inf)]
+        FpuCheckFSW X86_FSW_IE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0ValueConst xSP, REF(g_r80_Inf)
+
+        ; Invalid Operand (0/0) - Unmodified ST0.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Zero)]   }, [REF(g_r32_Zero)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_Zero)]   }, [REF(g_r64_Zero)]
+        FxSaveCheckFSW xSP, X86_FSW_IE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0ValueConst xSP, REF(g_r80_Zero)
+
+        ; Precision exception, rounded down.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Ten)]    }, [REF(g_r32_Ten)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_Three)]  }, [REF(g_r64_Three)]
+        FxSaveCheckFSW xSP, X86_FSW_PE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0Value_3_and_a_3rd(xSP)
+
+        ; Precision exception, rounded up.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     dword [REF(g_r32_Eleven)] }, [REF(g_r32_Eleven)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_Three)]  }, [REF(g_r64_Three)]
+        FxSaveCheckFSW xSP, X86_FSW_PE | X86_FSW_C1 | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0Value_3_and_two_3rds(xSP)
+
+        ; Overflow exception.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     tword [REF(g_r80_Max)]    }, [REF(g_r80_Max)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_0dot1)]  }, [REF(g_r64_0dot1)]
+        FxSaveCheckFSW xSP, X86_FSW_PE | X86_FSW_OE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0Value xSP, 0xfffffd7f, 0x9fffffff, 0x2002
+
+        ; Underflow exception.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     tword [REF(g_r80_Min)]    }, [REF(g_r80_Min)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_Ten)]    }, [REF(g_r64_Ten)]
+        FxSaveCheckFSW xSP, X86_FSW_PE | X86_FSW_UE | X86_FSW_C1 | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0Value xSP, 0xcccccccd, 0xcccccccc, 0x5ffd
+
+        ; Denormal operand - Unmodified ST0.
+        FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST
+        FpuCheckOpcodeCsIpDsDp { fld     tword [REF(g_r80_One)]    }, [REF(g_r80_One)]
+        FpuTrapOpcodeCsIpDsDp  { fdiv    qword [REF(g_r64_DnMax)]  }, [REF(g_r64_DnMax)]
+        FxSaveCheckFSW xSP, X86_FSW_DE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3
+        FxSaveCheckSt0ValueConst xSP, REF(g_r80_One)
+%endif
+
+
+        ; ## A couple of variations on the #PF theme. ##
+
+.success:
+        xor     eax, eax
+.return:
+        add     xSP, 2048
+        SAVE_ALL_EPILOGUE
+        ret
+
+ENDPROC     x861_TestFPUInstr1
+
+