Changeset 40143 in vbox

Timestamp:

Feb 16, 2012 10:08:06 AM (13 years ago)

Author:

vboxsync

Message:

fdiv - almost there...

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAll.cpp (modified) (2 diffs)
• VMMAll/IEMAllAImpl.asm (modified) (4 diffs)
• VMMAll/IEMAllInstructions.cpp.h (modified) (1 diff)
• include/IEMInternal.h (modified) (1 diff)
• testcase/tstIEMCheckMc.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -39 +39 @@
  *
  * The current code is very much work in progress. You've been warned!
+ *
+ *
+ * @section sec_iem_fpu_instr   FPU Instructions
+ *
+ * On x86 and AMD64 hosts, the FPU instructions are implemented by executing the
+ * same or equivalent instructions on the host FPU.  To make life easy, we also
+ * let the FPU prioritize the unmasked exceptions for us.  This however, only
+ * works reliably when CR0.NE is set, i.e. when using \#MF instead the IRQ 13
+ * for FPU exception delivery, because with CR0.NE=0 there is a window where we
+ * can trigger spurious FPU exceptions.
+ *
  *
  */
@@ -3529 +3540 @@
 
 
+/**
+ * Stores a result in a FPU register and updates the FSW and FTW.
+ *
+ * @param   pIemCpu             The IEM per CPU data.
+ * @param   pResult             The result to store.
+ * @param   iStReg              Which FPU register to store it in.
+ * @param   pCtx                The CPU context.
+ */
+static void iemFpuStoreResultOnly(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg, PCPUMCTX pCtx)
+{
+    Assert(iStReg < 8);
+    uint16_t  iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
+    pCtx->fpu.FSW &= X86_FSW_C_MASK;
+    pCtx->fpu.FSW |= pResult->FSW & ~X86_FSW_TOP_MASK;
+    pCtx->fpu.FTW |= RT_BIT(iReg);
+    pCtx->fpu.aRegs[iStReg].r80 = pResult->r80Result;
+}
+
+
+/**
+ * Stores a result in a FPU register, updates the FSW, FTW, FPUIP, FPUCS, and
+ * FOP.
+ *
+ * @param   pIemCpu             The IEM per CPU data.
+ * @param   pResult             The result to store.
+ * @param   iStReg              Which FPU register to store it in.
+ * @param   pCtx                The CPU context.
+ */
 static void iemFpuStoreResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg)
 {
-}
-
+    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
+    iemFpuUpdateOpcodeAndIP(pIemCpu, pCtx);
+    iemFpuStoreResultOnly(pIemCpu, pResult, iStReg, pCtx);
+}
+
+
+/**
+ * Stores a result in a FPU register, updates the FSW, FTW, FPUIP, FPUCS, FOP,
+ * FPUDP, and FPUDS.
+ *
+ * @param   pIemCpu             The IEM per CPU data.
+ * @param   pResult             The result to store.
+ * @param   iStReg              Which FPU register to store it in.
+ * @param   pCtx                The CPU context.
+ */
 static void iemFpuStoreResultWithMemOp(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)
 {
+    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
     iemFpuUpdateDP(pIemCpu, pIemCpu->CTX_SUFF(pCtx), iEffSeg, GCPtrEff);
-    //iemFpuStoreResult(pIemCpu, pResult);
+    iemFpuUpdateOpcodeAndIP(pIemCpu, pCtx);
+    iemFpuStoreResultOnly(pIemCpu, pResult, iStReg, pCtx);
 }
 

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -1281 +1281 @@
         fninit
         movzx   T0, word [%1 + X86FXSTATE.FCW]
+        and     T0, X86_FCW_MASK_ALL | X86_FCW_PC_MASK | X86_FCW_RC_MASK
         or      T0, X86_FCW_MASK_ALL
         mov     [xSP], T0
@@ -1287 +1288 @@
 
 ;;
+; Initialize the FPU for x87 operation, loading the guest's status word.
+;
+; @param    1       Expression giving the address of the FXSTATE of the guest.
+%macro FPU_INIT 1
+        fninit
+        movzx   T0, word [%1 + X86FXSTATE.FCW]
+        and     T0, X86_FCW_MASK_ALL | X86_FCW_PC_MASK | X86_FCW_RC_MASK
+        mov     [xSP], T0
+        fldcw   [xSP]
+%endmacro
+
+;;
 ; Need to move this as well somewhere better?
 ;
@@ -1323 +1336 @@
 ; @param    A0      FPU context (fxsave).
 ; @param    A1      Pointer to a IEMFPURESULT for the output.
-; @param    A2      Pointer to the 32-bit floating point value to convert.
+; @param    A2      Pointer to the 64-bit floating point value to convert.
 ;
 BEGINPROC_FASTCALL iemAImpl_fpu_r64_to_r80, 12
@@ -1339 +1352 @@
 ENDPROC iemAImpl_fpu_r64_to_r80
 
+
+;;
+; FDIV with 64-bit floating point value.
+;
+; @param    A0      FPU context (fxsave).
+; @param    A1      Pointer to a IEMFPURESULT for the output.
+; @param    A2      Pointer to the 80-bit dividend.
+; @param    A3      Pointer to the 64-bit divisor.
+;
+BEGINPROC_FASTCALL iemAImpl_fpu_fdiv_r80_by_r64, 16
+        PROLOGUE_4_ARGS
+        sub     xSP, 20h
+
+        FPU_INIT A0
+        fdiv    qword [A3]
+
+        fnstsw  word  [A1 + IEMFPURESULT.FSW]
+        fnclex
+        fstp    tword [A1 + IEMFPURESULT.r80Result]
+
+        add     xSP, 20h
+        EPILOGUE_4_ARGS 8
+ENDPROC iemAImpl_fpu_fdiv_r80_by_r64
+

trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

@@ -10842 +10842 @@
     IEM_MC_MAYBE_RAISE_FPU_XCPT();
     IEM_MC_FETCH_MEM_R64(r64Divisor, pIemCpu->iEffSeg, GCPtrEffSrc);
-    IEM_MC_REF_FPUREG_R80(pr80Dividend, 0);
-//    IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fpu_fdiv_r80_by_r64, pFpuRes, pr80Dividend, pr64Divisor);
+    IEM_MC_REF_FPUREG_R80(pr80Dividend, 0); /** @todo Check for and handle stack underflow! */
+    IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fpu_fdiv_r80_by_r64, pFpuRes, pr80Dividend, pr64Divisor);
 
     IEM_MC_STORE_FPU_RESULT_MEM_OP(FpuRes, 0, pIemCpu->iEffSeg, GCPtrEffSrc);

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -718 +718 @@
 /** @name FPU operations taking a 64-bit float argument
  * @{ */
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
 typedef FNIEMAIMPLFPUR64  *PFNIEMAIMPLFPUR64;
-FNIEMAIMPLFPUR64 iemAImpl_fpu_r64_to_r80;
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64U,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
+typedef FNIEMAIMPLFPUR64U  *PFNIEMAIMPLFPUR64U;
+FNIEMAIMPLFPUR64U iemAImpl_fpu_r64_to_r80;
+FNIEMAIMPLFPUR64  iemAImpl_fpu_fdiv_r80_by_r64;
+
 /** @} */
 

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -402 +402 @@
 
 #define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1)                     do { } while (0)
+#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a3)                 do { } while (0)
 #define IEM_MC_PUSH_FPU_RESULT(a_FpuData)                               do { } while (0)
 #define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { } while (0)