Changeset 40161 in vbox for trunk/src

Timestamp:

Feb 16, 2012 7:10:17 PM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

76314

Message:

IEM: Debugged fdiv, hacked my way around shortcuts in the recompiler FPU implementation.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAll.cpp (modified) (8 diffs)
• IEMAllAImpl.asm (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -3493 +3493 @@
         {
             /* No unmasked exceptions, just store the result. */
-            pCtx->fpu.FSW &= X86_FSW_TOP_MASK | X86_FSW_C0 | X86_FSW_C1 | X86_FSW_C2 | X86_FSW_C3;
-            pCtx->fpu.FSW |= (iNewTop << X86_FSW_TOP_SHIFT) | (pResult->FSW & ~(X86_FSW_TOP_MASK | X86_FSW_B | X86_FSW_ES));
+            pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C0 | X86_FSW_C1 | X86_FSW_C2 | X86_FSW_C3);
+            pCtx->fpu.FSW |= pResult->FSW & ~(X86_FSW_TOP_MASK | X86_FSW_B | X86_FSW_ES);
+            pCtx->fpu.FSW |= iNewTop << X86_FSW_TOP_SHIFT;
             pCtx->fpu.FTW |= RT_BIT(iNewTop);
             pCtx->fpu.aRegs[7].r80 = pResult->r80Result;
@@ -3507 +3508 @@
     {
         /* Masked stack overflow. */
-        pCtx->fpu.FSW &= X86_FSW_TOP_MASK | X86_FSW_C0 | X86_FSW_C1 | X86_FSW_C2 | X86_FSW_C3;
+        pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C0 | X86_FSW_C1 | X86_FSW_C2 | X86_FSW_C3);
         pCtx->fpu.FSW |= (iNewTop << X86_FSW_TOP_SHIFT) | X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
         pCtx->fpu.FTW |= RT_BIT(iNewTop);
@@ -3515 +3516 @@
     {
         /* Stack overflow exception. */
-        pCtx->fpu.FSW &= X86_FSW_C0 | X86_FSW_C1 | X86_FSW_C2 | X86_FSW_C3;
+        pCtx->fpu.FSW &= ~(X86_FSW_C0 | X86_FSW_C1 | X86_FSW_C2 | X86_FSW_C3);
         pCtx->fpu.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
         return;
@@ -3552 +3553 @@
     Assert(iStReg < 8);
     uint16_t  iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
-    pCtx->fpu.FSW &= X86_FSW_C_MASK;
+    pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
     pCtx->fpu.FSW |= pResult->FSW & ~X86_FSW_TOP_MASK;
     pCtx->fpu.FTW |= RT_BIT(iReg);
@@ -3601 +3602 @@
     {
         /* Masked underflow. */
-        pCtx->fpu.FSW &= X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3;
+        pCtx->fpu.FSW &= ~(X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3);
         pCtx->fpu.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
         pCtx->fpu.FTW |= RT_BIT(iReg);
@@ -3608 +3609 @@
     else
     {
-        pCtx->fpu.FSW &= X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3;
+        pCtx->fpu.FSW &= ~(X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3);
         pCtx->fpu.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
     }
 }
 
-static void iemFpuStackUnderflow(PIEMCPU pIemCpu, uint8_t iStReg)
+DECL_NO_INLINE(static, void) iemFpuStackUnderflow(PIEMCPU pIemCpu, uint8_t iStReg)
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
@@ -3620 +3621 @@
 }
 
-static void iemFpuStackUnderflowWithMemOp(PIEMCPU pIemCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)
+
+DECL_NO_INLINE(static, void)
+iemFpuStackUnderflowWithMemOp(PIEMCPU pIemCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
@@ -6752 +6755 @@
         } while (0)
 
+#if 1 /* The recompiler doesn't update these the intel way. */
+        pOrgCtx->fpu.FOP        = pDebugCtx->fpu.FOP;
+        pOrgCtx->fpu.FPUIP      = pDebugCtx->fpu.FPUIP;
+        pOrgCtx->fpu.CS         = pDebugCtx->fpu.CS;
+        pOrgCtx->fpu.Rsrvd1     = pDebugCtx->fpu.Rsrvd1;
+        pOrgCtx->fpu.FPUDP      = pDebugCtx->fpu.FPUDP;
+        pOrgCtx->fpu.DS         = pDebugCtx->fpu.DS;
+        pOrgCtx->fpu.Rsrvd2     = pDebugCtx->fpu.Rsrvd2;
+        pOrgCtx->fpu.MXCSR_MASK = pDebugCtx->fpu.MXCSR_MASK; /* only for the time being - old snapshots here. */
+        if ((pOrgCtx->fpu.FSW & X86_FSW_TOP_MASK) == (pDebugCtx->fpu.FSW & X86_FSW_TOP_MASK))
+            pOrgCtx->fpu.FSW = pDebugCtx->fpu.FSW;
+#endif
         if (memcmp(&pOrgCtx->fpu, &pDebugCtx->fpu, sizeof(pDebugCtx->fpu)))
         {

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -1288 +1288 @@
 
 ;;
-; Initialize the FPU for x87 operation, loading the guest's status word.
-;
+; Initialize the FPU for the actual instruction being emulated, this means
+; loading parts of the guest's control word and status word.
+;
+; @uses     24 bytes of stack.
 ; @param    1       Expression giving the address of the FXSTATE of the guest.
-%macro FPU_INIT 1
-        fninit
+;
+%macro FPU_LD_FXSTATE_FCW_AND_SAFE_FSW 1
+        fnstenv [xSP]
+
+        ; FCW - for exception, precision and rounding control.
         movzx   T0, word [%1 + X86FXSTATE.FCW]
         and     T0, X86_FCW_MASK_ALL | X86_FCW_PC_MASK | X86_FCW_RC_MASK
-        mov     [xSP], T0
-        fldcw   [xSP]
+        mov     [xSP + X86FSTENV32P.FCW], T0_16
+
+        ; FSW - for undefined C0, C1, C2, and C3.
+        movzx   T1, word [%1 + X86FXSTATE.FSW]
+        and     T1, X86_FSW_C_MASK
+        movzx   T0, word [xSP + X86FSTENV32P.FSW]
+        and     T0, X86_FSW_TOP_MASK
+        or      T0, T1
+        mov     [xSP + X86FSTENV32P.FSW], T0_16
+
+        fldenv  [xSP]
 %endmacro
+
 
 ;;
@@ -1365 +1380 @@
         sub     xSP, 20h
 
-        FPU_INIT A0
+        fninit
+        fld     tword [A2]
+        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
         fdiv    qword [A3]