Changeset 40163 in vbox
- Timestamp:
- Feb 16, 2012 8:28:18 PM (13 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
r40162 r40163 1369 1369 1370 1370 ;; 1371 ; FDIV with 64-bit floating point value. 1371 ; FPU instruction working on one 80-bit and one 64-bit floating point value. 1372 ; 1373 ; @param 1 The instruction 1372 1374 ; 1373 1375 ; @param A0 FPU context (fxsave). … … 1376 1378 ; @param A3 Pointer to the 64-bit divisor. 1377 1379 ; 1378 BEGINPROC_FASTCALL iemAImpl_fpu_fdiv_r80_by_r64, 16 1380 %macro IEMIMPL_FPU_R80_BY_R64 1 1381 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r64, 16 1379 1382 PROLOGUE_4_ARGS 1380 1383 sub xSP, 20h … … 1383 1386 fld tword [A2] 1384 1387 FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0 1385 fdivqword [A3]1388 %1 qword [A3] 1386 1389 1387 1390 fnstsw word [A1 + IEMFPURESULT.FSW] … … 1391 1394 add xSP, 20h 1392 1395 EPILOGUE_4_ARGS 8 1393 ENDPROC iemAImpl_fpu_fdiv_r80_by_r64 1394 1395 1396 ;; 1397 ; FMUL with 64-bit floating point value. 1398 ; 1399 ; @param A0 FPU context (fxsave). 1400 ; @param A1 Pointer to a IEMFPURESULT for the output. 1401 ; @param A2 Pointer to the 80-bit factor. 1402 ; @param A3 Pointer to the 64-bit factor. 1403 ; 1404 BEGINPROC_FASTCALL iemAImpl_fpu_fmul_r80_by_r64, 16 1405 PROLOGUE_4_ARGS 1406 sub xSP, 20h 1407 1408 fninit 1409 fld tword [A2] 1410 FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0 1411 fmul qword [A3] 1412 1413 fnstsw word [A1 + IEMFPURESULT.FSW] 1414 fnclex 1415 fstp tword [A1 + IEMFPURESULT.r80Result] 1416 1417 add xSP, 20h 1418 EPILOGUE_4_ARGS 8 1419 ENDPROC iemAImpl_fpu_fmul_r80_by_r64 1420 1396 ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r64 1397 %endmacro 1398 1399 IEMIMPL_FPU_R80_BY_R64 fadd 1400 IEMIMPL_FPU_R80_BY_R64 fmul 1401 IEMIMPL_FPU_R80_BY_R64 fcom 1402 IEMIMPL_FPU_R80_BY_R64 fsub 1403 IEMIMPL_FPU_R80_BY_R64 fsubr 1404 IEMIMPL_FPU_R80_BY_R64 fdiv 1405 IEMIMPL_FPU_R80_BY_R64 fdivr 1406 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h
r40162 r40163 10806 10806 FNIEMOP_STUB_1(iemOp_fdiv_stN_st0, uint8_t, bRm); 10807 10807 10808 /** Opcode 0xdc !11/0. */ 10809 FNIEMOP_STUB_1(iemOp_fadd_m64r, uint8_t, bRm); 10810 10811 /** Opcode 0xdc !11/1. */ 10812 FNIEMOP_DEF_1(iemOp_fmul_m64r, uint8_t, bRm) 10813 { 10814 IEMOP_MNEMONIC("fdiv m64r"); 10808 10809 /** 10810 * Common worker for FPU instructions working on ST0 and a 64-bit floating point 10811 * memory operand, and storing the result in ST0. 10812 * 10813 * @param pImpl Pointer to the instruction implementation (assembly). 10814 */ 10815 FNIEMOP_DEF_2(iemOpHlpFpu_ST0_m64r, uint8_t, bRm, PFNIEMAIMPLFPUR64, pfnImpl) 10816 { 10815 10817 IEMOP_HLP_NO_LOCK_PREFIX(); 10816 10818 … … 10828 10830 IEM_MC_FETCH_MEM_R64(r64Factor2, pIemCpu->iEffSeg, GCPtrEffSrc); 10829 10831 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Factor1, 0) 10830 IEM_MC_CALL_FPU_AIMPL_3( iemAImpl_fpu_fmul_r80_by_r64, pFpuRes, pr80Factor1, pr64Factor2);10832 IEM_MC_CALL_FPU_AIMPL_3(pfnImpl, pFpuRes, pr80Factor1, pr64Factor2); 10831 10833 IEM_MC_STORE_FPU_RESULT_MEM_OP(FpuRes, 0, pIemCpu->iEffSeg, GCPtrEffSrc); 10832 10834 IEM_MC_ELSE() … … 10839 10841 } 10840 10842 10843 10844 /** Opcode 0xdc !11/0. */ 10845 FNIEMOP_DEF_1(iemOp_fadd_m64r, uint8_t, bRm) 10846 { 10847 IEMOP_MNEMONIC("fadd m64r"); 10848 return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fadd_r80_by_r64); 10849 } 10850 10851 10852 /** Opcode 0xdc !11/1. */ 10853 FNIEMOP_DEF_1(iemOp_fmul_m64r, uint8_t, bRm) 10854 { 10855 IEMOP_MNEMONIC("fmul m64r"); 10856 return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fmul_r80_by_r64); 10857 } 10858 10841 10859 /** Opcode 0xdc !11/2. */ 10842 FNIEMOP_STUB_1(iemOp_fcom_m64r, uint8_t, bRm); 10860 FNIEMOP_DEF_1(iemOp_fcom_m64r, uint8_t, bRm) 10861 { 10862 IEMOP_MNEMONIC("fcom m64r"); 10863 return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fcom_r80_by_r64); 10864 } 10865 10843 10866 10844 10867 /** Opcode 0xdc !11/3. */ 10845 10868 FNIEMOP_STUB_1(iemOp_fcomp_m64r, uint8_t, bRm); 10846 10869 10870 10847 10871 /** Opcode 0xdc !11/4. */ 10848 FNIEMOP_STUB_1(iemOp_fsub_m64r, uint8_t, bRm); 10872 FNIEMOP_DEF_1(iemOp_fsub_m64r, uint8_t, bRm) 10873 { 10874 IEMOP_MNEMONIC("fsub m64r"); 10875 return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fsub_r80_by_r64); 10876 } 10877 10849 10878 10850 10879 /** Opcode 0xdc !11/5. */ 10851 FNIEMOP_STUB_1(iemOp_fsubr_m64r, uint8_t, bRm); 10880 FNIEMOP_DEF_1(iemOp_fsubr_m64r, uint8_t, bRm) 10881 { 10882 IEMOP_MNEMONIC("fsubr m64r"); 10883 return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fsubr_r80_by_r64); 10884 } 10852 10885 10853 10886 … … 10856 10889 { 10857 10890 IEMOP_MNEMONIC("fdiv m64r"); 10858 IEMOP_HLP_NO_LOCK_PREFIX(); 10859 10860 IEM_MC_BEGIN(3, 3); 10861 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 10862 IEM_MC_LOCAL(IEMFPURESULT, FpuRes); 10863 IEM_MC_LOCAL(RTFLOAT64U, r64Divisor); 10864 IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0); 10865 IEM_MC_ARG(PCRTFLOAT80U, pr80Dividend, 1); 10866 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Divisor, r64Divisor, 2); 10867 10868 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm); 10869 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 10870 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 10871 IEM_MC_FETCH_MEM_R64(r64Divisor, pIemCpu->iEffSeg, GCPtrEffSrc); 10872 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Dividend, 0) 10873 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fpu_fdiv_r80_by_r64, pFpuRes, pr80Dividend, pr64Divisor); 10874 IEM_MC_STORE_FPU_RESULT_MEM_OP(FpuRes, 0, pIemCpu->iEffSeg, GCPtrEffSrc); 10875 IEM_MC_ELSE() 10876 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(0, pIemCpu->iEffSeg, GCPtrEffSrc); 10877 IEM_MC_ENDIF(); 10878 IEM_MC_ADVANCE_RIP(); 10879 10880 IEM_MC_END(); 10881 return VINF_SUCCESS; 10891 return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fdiv_r80_by_r64); 10882 10892 } 10883 10893 10884 10894 10885 10895 /** Opcode 0xdc !11/7. */ 10886 FNIEMOP_STUB_1(iemOp_fdivr_m64r, uint8_t, bRm); 10896 FNIEMOP_DEF_1(iemOp_fdivr_m64r, uint8_t, bRm) 10897 { 10898 IEMOP_MNEMONIC("fdivr m64r"); 10899 return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fdivr_r80_by_r64); 10900 } 10887 10901 10888 10902 -
trunk/src/VBox/VMM/include/IEMInternal.h
r40162 r40163 724 724 typedef FNIEMAIMPLFPUR64U *PFNIEMAIMPLFPUR64U; 725 725 FNIEMAIMPLFPUR64U iemAImpl_fpu_r64_to_r80; 726 FNIEMAIMPLFPUR64 iemAImpl_fpu_fdiv_r80_by_r64; 727 FNIEMAIMPLFPUR64 iemAImpl_fpu_fmul_r80_by_r64; 726 FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64; 727 FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64; 728 FNIEMAIMPLFPUR64 iemAImpl_fcom_r80_by_r64; 729 FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64; 730 FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64; 731 FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64; 732 FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64; 728 733 729 734 /** @} */ -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r40154 r40163 432 432 #define IEM_MC_ENDIF() } do {} while (0) 433 433 434 435 #define iemAImpl_fpu_r64_to_r80 NULL 436 #define iemAImpl_fadd_r80_by_r64 NULL 437 #define iemAImpl_fmul_r80_by_r64 NULL 438 #define iemAImpl_fcom_r80_by_r64 NULL 439 #define iemAImpl_fsub_r80_by_r64 NULL 440 #define iemAImpl_fsubr_r80_by_r64 NULL 441 #define iemAImpl_fdiv_r80_by_r64 NULL 442 #define iemAImpl_fdivr_r80_by_r64 NULL 443 444 434 445 /** @} */ 435 446
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