Changeset 40227 in vbox for trunk/src/VBox/HostDrivers

Timestamp:

Feb 23, 2012 11:15:37 AM (13 years ago)

Author:

vboxsync

Message:

VMM/VMMR0 SupDrv Solaris/MpNotification: Fix guru meditation/panics when host CPUs are dynamically offline'd/online'd. More flexibility if offline notifications don't fire on the desired CPU.

File:

• trunk/src/VBox/HostDrivers/Support/SUPDrv.c (modified) (8 diffs)

trunk/src/VBox/HostDrivers/Support/SUPDrv.c

@@ -138 +138 @@
 static void                 supdrvGipUpdatePerCpu(PSUPGLOBALINFOPAGE pGip, uint64_t u64NanoTS, uint64_t u64TSC,
                                                   RTCPUID idCpu, uint8_t idApic, uint64_t iTick);
+static void                 supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS);
 
 
@@ -5039 +5040 @@
     uint16_t    idApic = UINT16_MAX;
     uint32_t    i = 0;
+    uint64_t    u64NanoTS = 0;
 
     AssertRelease(idCpu == RTMpCpuId());
@@ -5059 +5061 @@
      * Update the entry.
      */
+    u64NanoTS = RTTimeSystemNanoTS() - pGip->u32UpdateIntervalNS;
     i = supdrvGipCpuIndexFromCpuId(pGip, idCpu);
+    supdrvGipInitCpu(pGip, &pGip->aCPUs[i], u64NanoTS);
     idApic = ASMGetApicId();
     ASMAtomicUoWriteU16(&pGip->aCPUs[i].idApic,  idApic);
@@ -5113 +5117 @@
  * @param   idCpu       The cpu it applies to.
  * @param   pvUser      Pointer to the device extension.
+ *
+ * @remarks This function -must- fire on the newly online'd CPU for the
+ *          RTMPEVENT_ONLINE case and can fire on any CPU for the
+ *          RTMPEVENT_OFFLINE case.
  */
 static DECLCALLBACK(void) supdrvGipMpEvent(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvUser)
@@ -5119 +5127 @@
     PSUPGLOBALINFOPAGE  pGip    = pDevExt->pGip;
 
-    AssertRelease(idCpu == RTMpCpuId());
     AssertRelease(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
 
@@ -5130 +5137 @@
         {
             case RTMPEVENT_ONLINE:
+                AssertRelease(idCpu == RTMpCpuId());
                 supdrvGipMpEventOnline(pGip, idCpu);
                 break;
@@ -5328 +5336 @@
 }
 
+
+/**
+ * Initializes per-CPU GIP information.
+ *
+ * @param   pGip        Pointer to the read-write kernel mapping of the GIP.
+ * @param   pCpu        Pointer to which GIP CPU to initalize.
+ * @param   u64NanoTS   The current nanosecond timestamp.
+ */
+static void supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS)
+{
+    pCpu->u32TransactionId   = 2;
+    pCpu->u64NanoTS          = u64NanoTS;
+    pCpu->u64TSC             = ASMReadTSC();
+
+    pCpu->enmState           = SUPGIPCPUSTATE_INVALID;
+    pCpu->idCpu              = NIL_RTCPUID;
+    pCpu->iCpuSet            = -1;
+    pCpu->idApic             = UINT16_MAX;
+
+    /*
+     * We don't know the following values until we've executed updates.
+     * So, we'll just pretend it's a 4 GHz CPU and adjust the history it on
+     * the 2nd timer callout.
+     */
+    pCpu->u64CpuHz          = _4G + 1; /* tstGIP-2 depends on this. */
+    pCpu->u32UpdateIntervalTSC
+        = pCpu->au32TSCHistory[0]
+        = pCpu->au32TSCHistory[1]
+        = pCpu->au32TSCHistory[2]
+        = pCpu->au32TSCHistory[3]
+        = pCpu->au32TSCHistory[4]
+        = pCpu->au32TSCHistory[5]
+        = pCpu->au32TSCHistory[6]
+        = pCpu->au32TSCHistory[7]
+        = (uint32_t)(_4G / pGip->u32UpdateHz);
+}
 
 
@@ -5376 +5420 @@
 
     for (i = 0; i < cCpus; i++)
-    {
-        pGip->aCPUs[i].u32TransactionId  = 2;
-        pGip->aCPUs[i].u64NanoTS         = u64NanoTS;
-        pGip->aCPUs[i].u64TSC            = ASMReadTSC();
-
-        pGip->aCPUs[i].enmState          = SUPGIPCPUSTATE_INVALID;
-        pGip->aCPUs[i].idCpu             = NIL_RTCPUID;
-        pGip->aCPUs[i].iCpuSet           = -1;
-        pGip->aCPUs[i].idApic            = UINT16_MAX;
-
-        /*
-         * We don't know the following values until we've executed updates.
-         * So, we'll just pretend it's a 4 GHz CPU and adjust the history it on
-         * the 2nd timer callout.
-         */
-        pGip->aCPUs[i].u64CpuHz          = _4G + 1; /* tstGIP-2 depends on this. */
-        pGip->aCPUs[i].u32UpdateIntervalTSC
-            = pGip->aCPUs[i].au32TSCHistory[0]
-            = pGip->aCPUs[i].au32TSCHistory[1]
-            = pGip->aCPUs[i].au32TSCHistory[2]
-            = pGip->aCPUs[i].au32TSCHistory[3]
-            = pGip->aCPUs[i].au32TSCHistory[4]
-            = pGip->aCPUs[i].au32TSCHistory[5]
-            = pGip->aCPUs[i].au32TSCHistory[6]
-            = pGip->aCPUs[i].au32TSCHistory[7]
-            = /*pGip->aCPUs[i].u64CpuHz*/ (uint32_t)(_4G / uUpdateHz);
-    }
+        supdrvGipInitCpu(pGip, &pGip->aCPUs[i], u64NanoTS);
 
     /*