Changeset 40244 in vbox

Timestamp:

Feb 24, 2012 12:48:47 AM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

76454

Message:

IEM: Implemented FPU instructions 0xd9 0xf3 thru 0xd9 0xff, completing the 0xd9 prefixed instructions.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl.asm (modified) (6 diffs)
• VMMAll/IEMAllCImpl.cpp.h (modified) (1 diff)
• VMMAll/IEMAllInstructions.cpp.h (modified) (4 diffs)
• include/IEMInternal.h (modified) (3 diffs)
• testcase/tstIEMCheckMc.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -1609 +1609 @@
 ; @param    A0      FPU context (fxsave).
 ; @param    A1      Pointer to a IEMFPURESULT for the output.
+; @param    A2      Pointer to the first 80-bit value (ST0)
+; @param    A3      Pointer to the second 80-bit value (STn).
+;
+%macro IEMIMPL_FPU_R80_BY_R80 2
+BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
+        PROLOGUE_4_ARGS
+        sub     xSP, 20h
+
+        fninit
+        fld     tword [A3]
+        fld     tword [A2]
+        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
+        %1      %2
+
+        fnstsw  word  [A1 + IEMFPURESULT.FSW]
+        fnclex
+        fstp    tword [A1 + IEMFPURESULT.r80Result]
+
+        fninit
+        add     xSP, 20h
+        EPILOGUE_4_ARGS 8
+ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
+%endmacro
+
+IEMIMPL_FPU_R80_BY_R80 fadd,   {st0, st1}
+IEMIMPL_FPU_R80_BY_R80 fmul,   {st0, st1}
+IEMIMPL_FPU_R80_BY_R80 fsub,   {st0, st1}
+IEMIMPL_FPU_R80_BY_R80 fsubr,  {st0, st1}
+IEMIMPL_FPU_R80_BY_R80 fdiv,   {st0, st1}
+IEMIMPL_FPU_R80_BY_R80 fdivr,  {st0, st1}
+IEMIMPL_FPU_R80_BY_R80 fprem,  {}
+IEMIMPL_FPU_R80_BY_R80 fprem1, {}
+IEMIMPL_FPU_R80_BY_R80 fscale, {}
+
+
+;;
+; FPU instruction working on two 80-bit floating point values, ST1 and ST0,
+; storing the result in ST1 and popping the stack.
+;
+; @param    1       The instruction
+;
+; @param    A0      FPU context (fxsave).
+; @param    A1      Pointer to a IEMFPURESULT for the output.
+; @param    A2      Pointer to the first 80-bit value (ST1).
+; @param    A3      Pointer to the second 80-bit value (ST0).
+;
+%macro IEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP 1
+BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
+        PROLOGUE_4_ARGS
+        sub     xSP, 20h
+
+        fninit
+        fld     tword [A2]
+        fld     tword [A3]
+        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
+        %1
+
+        fnstsw  word  [A1 + IEMFPURESULT.FSW]
+        fnclex
+        fstp    tword [A1 + IEMFPURESULT.r80Result]
+
+        fninit
+        add     xSP, 20h
+        EPILOGUE_4_ARGS 8
+ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
+%endmacro
+
+IEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP fpatan
+IEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP fyl2xp1
+
+
+;;
+; FPU instruction working on two 80-bit floating point values, only
+; returning FSW.
+;
+; @param    1       The instruction
+;
+; @param    A0      FPU context (fxsave).
+; @param    A1      Pointer to a uint16_t for the resulting FSW.
 ; @param    A2      Pointer to the first 80-bit value.
 ; @param    A3      Pointer to the second 80-bit value.
 ;
-%macro IEMIMPL_FPU_R80_BY_R80 1
+%macro IEMIMPL_FPU_R80_BY_R80_FSW 1
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
         PROLOGUE_4_ARGS
@@ -1623 +1702 @@
         %1      st0, st1
 
-        fnstsw  word  [A1 + IEMFPURESULT.FSW]
-        fnclex
-        fstp    tword [A1 + IEMFPURESULT.r80Result]
-
-        fninit
-        add     xSP, 20h
-        EPILOGUE_4_ARGS 8
-ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
-%endmacro
-
-IEMIMPL_FPU_R80_BY_R80 fadd
-IEMIMPL_FPU_R80_BY_R80 fmul
-IEMIMPL_FPU_R80_BY_R80 fsub
-IEMIMPL_FPU_R80_BY_R80 fsubr
-IEMIMPL_FPU_R80_BY_R80 fdiv
-IEMIMPL_FPU_R80_BY_R80 fdivr
-
-
-;;
-; FPU instruction working on two 80-bit floating point values, only
-; returning FSW.
-;
-; @param    1       The instruction
-;
-; @param    A0      FPU context (fxsave).
-; @param    A1      Pointer to a uint16_t for the resulting FSW.
-; @param    A2      Pointer to the first 80-bit value.
-; @param    A3      Pointer to the second 80-bit value.
-;
-%macro IEMIMPL_FPU_R80_BY_R80_FSW 1
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
-        PROLOGUE_4_ARGS
-        sub     xSP, 20h
-
-        fninit
-        fld     tword [A3]
-        fld     tword [A2]
-        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
-        %1      st0, st1
-
         fnstsw  word  [A1]
 
@@ -1708 +1747 @@
 IEMIMPL_FPU_R80 f2xm1
 IEMIMPL_FPU_R80 fyl2x
+IEMIMPL_FPU_R80 fsqrt
+IEMIMPL_FPU_R80 frndint
+IEMIMPL_FPU_R80 fsin
+IEMIMPL_FPU_R80 fcos
 
 
@@ -1788 +1831 @@
 ; @param    A2      Pointer to the 80-bit value.
 ;
-BEGINPROC_FASTCALL iemAImpl_fptan_r80_r80, 12
+%macro IEMIMPL_FPU_R80_R80 1
+BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_r80, 12
         PROLOGUE_3_ARGS
         sub     xSP, 20h
@@ -1795 +1839 @@
         fld     tword [A2]
         FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
-        fptan
+        %1
 
         fnstsw  word  [A1 + IEMFPURESULTTWO.FSW]
@@ -1806 +1850 @@
         add     xSP, 20h
         EPILOGUE_3_ARGS 4
-ENDPROC iemAImpl_fptan_r80_r80
-
+ENDPROC iemAImpl_ %+ %1 %+ _r80_r80
+%endmacro
+
+IEMIMPL_FPU_R80_R80 fptan
+IEMIMPL_FPU_R80_R80 fxtract
+IEMIMPL_FPU_R80_R80 fsincos
+

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -4306 +4306 @@
 }
 
+
+/**
+ * Implements 'FINCSTP' and 'FDECSTP'.
+ *
+ * @param   cToAdd              1 or 7.
+ */
+IEM_CIMPL_DEF_1(iemCImpl_fpu_AddToTop, uint8_t, cToAdd)
+{
+    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
+
+    /*
+     * Raise exceptions.
+     */
+    if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
+        return iemRaiseDeviceNotAvailable(pIemCpu);
+    uint16_t u16Fsw = pCtx->fpu.FSW;
+    if (u16Fsw & X86_FSW_ES)
+        return iemRaiseMathFault(pIemCpu);
+
+    /*
+     * Do the job.
+     *
+     * Note! The instructions are listed as control instructions and should
+     *       therefore not update FOP, FPUIP and FPUCS...
+     * Note! C0, C2 and C3 are documented as undefined, we clear them.
+     */
+    /** @todo Testcase: Check whether FOP, FPUIP and FPUCS are affected by
+     *        FINCSTP and FDECSTP. */
+    uint16_t iTop = X86_FSW_TOP_GET(u16Fsw);
+    iTop += cToAdd;
+    iTop &= X86_FSW_TOP_SMASK;
+    u16Fsw &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
+    u16Fsw |= (iTop << X86_FSW_TOP_SHIFT);
+    pCtx->fpu.FSW = u16Fsw;
+
+    return VINF_SUCCESS;
+}
+
+
 /** @} */
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

@@ -11067 +11067 @@
 
 
-/** Opcode 0xd9 0xf2. */
-FNIEMOP_DEF(iemOp_fptan)
-{
-    IEMOP_MNEMONIC("fptan st0");
+/**
+ * Common worker for FPU instructions working on ST0 and having two outputs, one
+ * replacing ST0 and one pushed onto the stack.
+ *
+ * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
+ */
+FNIEMOP_DEF_1(iemOpHlpFpuReplace_st0_push, PFNIEMAIMPLFPUR80UNARYTWO, pfnAImpl)
+{
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
@@ -11081 +11085 @@
     IEM_MC_MAYBE_RAISE_FPU_XCPT();
     IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
-        IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fptan_r80_r80, pFpuResTwo, pr80Value);
+        IEM_MC_CALL_FPU_AIMPL_2(pfnAImpl, pFpuResTwo, pr80Value);
         IEM_MC_PUSH_FPU_RESULT_TWO(FpuResTwo);
     IEM_MC_ELSE()
@@ -11090 +11094 @@
     IEM_MC_END();
     return VINF_SUCCESS;
-
-}
+}
+
+
+/** Opcode 0xd9 0xf2. */
+FNIEMOP_DEF(iemOp_fptan)
+{
+    IEMOP_MNEMONIC("fptan st0");
+    return FNIEMOP_CALL_1(iemOpHlpFpuReplace_st0_push, iemAImpl_fptan_r80_r80);
+}
+
+
+/**
+ * Common worker for FPU instructions working on STn and ST0, storing the result
+ * in STn, and popping the stack unless IE, DE or ZE was raised.
+ *
+ * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
+ */
+FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
+{
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+
+    IEM_MC_BEGIN(3, 1);
+    IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
+    IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes,        FpuRes,     0);
+    IEM_MC_ARG(PCRTFLOAT80U,            pr80Value1,                 1);
+    IEM_MC_ARG(PCRTFLOAT80U,            pr80Value2,                 2);
+
+    IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
+    IEM_MC_MAYBE_RAISE_FPU_XCPT();
+
+    IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, bRm & X86_MODRM_RM_MASK, pr80Value2, 0)
+        IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2);
+        IEM_MC_STORE_FPU_RESULT_THEN_POP(FpuRes, bRm & X86_MODRM_RM_MASK);
+    IEM_MC_ELSE()
+        IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(bRm & X86_MODRM_RM_MASK);
+    IEM_MC_ENDIF();
+    IEM_MC_ADVANCE_RIP();
+
+    IEM_MC_END();
+    return VINF_SUCCESS;
+}
+
 
 /** Opcode 0xd9 0xf3. */
-FNIEMOP_STUB(iemOp_fpatan);
+FNIEMOP_DEF(iemOp_fpatan)
+{
+    IEMOP_MNEMONIC("fpatan st1,st0");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, 1, iemAImpl_fpatan_r80_by_r80);
+}
+
 
 /** Opcode 0xd9 0xf4. */
-FNIEMOP_STUB(iemOp_fxtract);
+FNIEMOP_DEF(iemOp_fxtract)
+{
+    IEMOP_MNEMONIC("fxtract st0");
+    return FNIEMOP_CALL_1(iemOpHlpFpuReplace_st0_push, iemAImpl_fxtract_r80_r80);
+}
+
 
 /** Opcode 0xd9 0xf5. */
-FNIEMOP_STUB(iemOp_fprem1);
+FNIEMOP_DEF(iemOp_fprem1)
+{
+    IEMOP_MNEMONIC("fprem1 st0, st1");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, 1, iemAImpl_fprem1_r80_by_r80);
+}
+
 
 /** Opcode 0xd9 0xf6. */
-FNIEMOP_STUB(iemOp_fdecstp);
+FNIEMOP_DEF(iemOp_fdecstp)
+{
+    IEMOP_MNEMONIC("fdecstp");
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+    return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_fpu_AddToTop, 7);
+}
+
 
 /** Opcode 0xd9 0xf7. */
-FNIEMOP_STUB(iemOp_fincstp);
+FNIEMOP_DEF(iemOp_fincstp)
+{
+    IEMOP_MNEMONIC("fincstp");
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+    return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_fpu_AddToTop, 1);
+}
+
 
 /** Opcode 0xd9 0xf8. */
-FNIEMOP_STUB(iemOp_fprem);
+FNIEMOP_DEF(iemOp_fprem)
+{
+    IEMOP_MNEMONIC("fprem st0, st1");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, 1, iemAImpl_fprem_r80_by_r80);
+}
+
 
 /** Opcode 0xd9 0xf9. */
-FNIEMOP_STUB(iemOp_fyl2xp1);
+FNIEMOP_DEF(iemOp_fyl2xp1)
+{
+    IEMOP_MNEMONIC("fyl2xp1 st1,st0");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, 1, iemAImpl_fyl2xp1_r80_by_r80);
+}
+
 
 /** Opcode 0xd9 0xfa. */
-FNIEMOP_STUB(iemOp_fsqrt);
+FNIEMOP_DEF(iemOp_fsqrt)
+{
+    IEMOP_MNEMONIC("fsqrt st0");
+    return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fsqrt_r80);
+}
+
 
 /** Opcode 0xd9 0xfb. */
-FNIEMOP_STUB(iemOp_fsincos);
+FNIEMOP_DEF(iemOp_fsincos)
+{
+    IEMOP_MNEMONIC("fsincos st0");
+    return FNIEMOP_CALL_1(iemOpHlpFpuReplace_st0_push, iemAImpl_fsincos_r80_r80);
+}
+
 
 /** Opcode 0xd9 0xfc. */
-FNIEMOP_STUB(iemOp_frndint);
+FNIEMOP_DEF(iemOp_frndint)
+{
+    IEMOP_MNEMONIC("frndint st0");
+    return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_frndint_r80);
+}
+
 
 /** Opcode 0xd9 0xfd. */
-FNIEMOP_STUB(iemOp_fscale);
+FNIEMOP_DEF(iemOp_fscale)
+{
+    IEMOP_MNEMONIC("fscale st0, st1");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, 1, iemAImpl_fscale_r80_by_r80);
+}
+
 
 /** Opcode 0xd9 0xfe. */
-FNIEMOP_STUB(iemOp_fsin);
+FNIEMOP_DEF(iemOp_fsin)
+{
+    IEMOP_MNEMONIC("fsin st0");
+    return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fsin_r80);
+}
+
 
 /** Opcode 0xd9 0xff. */
-FNIEMOP_STUB(iemOp_fcos);
+FNIEMOP_DEF(iemOp_fcos)
+{
+    IEMOP_MNEMONIC("fcos st0");
+    return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fcos_r80);
+}
 
 
@@ -11787 +11897 @@
         }
     }
-}
-
-
-/**
- * Common worker for FPU instructions working on STn and ST0, storing the result
- * in STn, and poping the stack unless IE, DE or ZE was raised.
- *
- * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
- */
-FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
-{
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-    IEM_MC_BEGIN(3, 1);
-    IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
-    IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes,        FpuRes,     0);
-    IEM_MC_ARG(PCRTFLOAT80U,            pr80Value1,                 1);
-    IEM_MC_ARG(PCRTFLOAT80U,            pr80Value2,                 2);
-
-    IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
-    IEM_MC_MAYBE_RAISE_FPU_XCPT();
-
-    IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, bRm & X86_MODRM_RM_MASK, pr80Value2, 0)
-        IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2);
-        IEM_MC_STORE_FPU_RESULT_THEN_POP(FpuRes, bRm & X86_MODRM_RM_MASK);
-    IEM_MC_ELSE()
-        IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(bRm & X86_MODRM_RM_MASK);
-    IEM_MC_ENDIF();
-    IEM_MC_ADVANCE_RIP();
-
-    IEM_MC_END();
-    return VINF_SUCCESS;
 }
 

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -799 +799 @@
 FNIEMAIMPLFPUR80            iemAImpl_fdiv_r80_by_r80;
 FNIEMAIMPLFPUR80            iemAImpl_fdivr_r80_by_r80;
+FNIEMAIMPLFPUR80            iemAImpl_fprem_r80_by_r80;
+FNIEMAIMPLFPUR80            iemAImpl_fprem1_r80_by_r80;
+FNIEMAIMPLFPUR80            iemAImpl_fscale_r80_by_r80;
+
+FNIEMAIMPLFPUR80            iemAImpl_fpatan_r80_by_r80;
+FNIEMAIMPLFPUR80            iemAImpl_fyl2xp1_r80_by_r80;
 
 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
@@ -811 +817 @@
 FNIEMAIMPLFPUR80UNARY       iemAImpl_f2xm1_r80;
 FNIEMAIMPLFPUR80UNARY       iemAImpl_fyl2x_r80;
+FNIEMAIMPLFPUR80UNARY       iemAImpl_fsqrt_r80;
+FNIEMAIMPLFPUR80UNARY       iemAImpl_frndint_r80;
+FNIEMAIMPLFPUR80UNARY       iemAImpl_fsin_r80;
+FNIEMAIMPLFPUR80UNARY       iemAImpl_fcos_r80;
 
 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
@@ -827 +837 @@
 FNIEMAIMPLFPUR80LDCONST     iemAImpl_fldz;
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_fptan_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val));
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
+                                                           PCRTFLOAT80U pr80Val));
+typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
+FNIEMAIMPLFPUR80UNARYTWO    iemAImpl_fptan_r80_r80;
+FNIEMAIMPLFPUR80UNARYTWO    iemAImpl_fxtract_r80_r80;
+FNIEMAIMPLFPUR80UNARYTWO    iemAImpl_fsincos_r80_r80;
 
 /** @} */

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -185 +185 @@
 #define iemAImpl_fdiv_r80_by_r80        NULL
 #define iemAImpl_fdivr_r80_by_r80       NULL
+#define iemAImpl_fprem_r80_by_r80       NULL
+#define iemAImpl_fprem1_r80_by_r80      NULL
+#define iemAImpl_fscale_r80_by_r80      NULL
+
+#define iemAImpl_fpatan_r80_by_r80      NULL
+#define iemAImpl_fyl2xp1_r80_by_r80     NULL
+
 #define iemAImpl_fcom_r80_by_r80        NULL
 #define iemAImpl_fabs_r80               NULL
@@ -192 +199 @@
 #define iemAImpl_f2xm1_r80              NULL
 #define iemAImpl_fyl2x_r80              NULL
+#define iemAImpl_fsqrt_r80              NULL
+#define iemAImpl_frndint_r80            NULL
+#define iemAImpl_fsin_r80               NULL
+#define iemAImpl_fcos_r80               NULL
+
 #define iemAImpl_fld1                   NULL
 #define iemAImpl_fldl2t                 NULL
@@ -199 +211 @@
 #define iemAImpl_fldln2                 NULL
 #define iemAImpl_fldz                   NULL
+
+#define iemAImpl_fptan_r80_r80          NULL
+#define iemAImpl_fxtract_r80_r80        NULL
+#define iemAImpl_fsincos_r80_r80        NULL
 
 #define iemCImpl_callf                  NULL