Changeset 40247 in vbox

Timestamp:

Feb 24, 2012 12:59:44 PM (13 years ago)

Author:

vboxsync

Message:

IEM: Completed FPU instruction starting with 0xdb. Fixed build break from previous commit.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAll.cpp (modified) (5 diffs)
• VMMAll/IEMAllAImpl.asm (modified) (3 diffs)
• VMMAll/IEMAllInstructions.cpp.h (modified) (9 diffs)
• include/IEMInternal.h (modified) (2 diffs)
• testcase/tstIEMCheckMc.cpp (modified) (5 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -3729 +3729 @@
 
 /**
+ * Updates the FSW, FOP, FPUIP, and FPUCS, then pops the stack twice.
+ *
+ * @param   pIemCpu             The IEM per CPU data.
+ * @param   u16FSW              The FSW from the current instruction.
+ */
+static void iemFpuUpdateFSWThenPopPop(PIEMCPU pIemCpu, uint16_t u16FSW)
+{
+    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
+    iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
+    iemFpuUpdateFSWOnly(pCtx, u16FSW);
+    iemFpuMaybePopOne(pCtx);
+    iemFpuMaybePopOne(pCtx);
+}
+
+
+/**
  * Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS, then pops the stack.
  *
@@ -3818 +3834 @@
     iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
     iemFpuStackUnderflowOnly(pIemCpu, iStReg, pCtx);
+    iemFpuMaybePopOne(pCtx);
+}
+
+
+DECL_NO_INLINE(static, void) iemFpuStackUnderflowThenPopPop(PIEMCPU pIemCpu)
+{
+    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
+    iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
+    iemFpuStackUnderflowOnly(pIemCpu, UINT8_MAX, pCtx);
+    iemFpuMaybePopOne(pCtx);
     iemFpuMaybePopOne(pCtx);
 }
@@ -5974 +6000 @@
 #define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
     IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
+#define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
+    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
 
 #define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
@@ -6320 +6348 @@
 #define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
     iemFpuUpdateFSWWithMemOpThenPop(pIemCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
+/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
+#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
+    iemFpuUpdateFSWThenPop(pIemCpu, a_u16FSW)
 
 /** Raises a FPU stack underflow exception.  Sets FPUIP, FPUCS and FOP. */
@@ -6336 +6367 @@
 #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
     iemFpuStackUnderflowWithMemOpThenPop(pIemCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
+/** Raises a FPU stack underflow exception.  Sets FPUIP, FPUCS and FOP. Pops
+ *  stack twice. */
+#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
+    iemFpuStackUnderflowThenPopPop(pIemCpu)
 /** Raises a FPU stack underflow exception for an instruction pushing a result
  *  value onto the stack. Sets FPUIP, FPUCS and FOP. */

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -1324 +1324 @@
 
 
+;
+;---------------------- 32-bit signed integer operations ----------------------
+;
+
+
 ;;
 ; Converts a 80-bit floating point value to a 32-bit signed integer.
@@ -1348 +1353 @@
 ENDPROC iemAImpl_fpu_r80_to_i32
 
+
+;;
+; Store a 80-bit floating point value (register) as a 32-bit signed integer (memory).
+;
+; @param    A0      FPU context (fxsave).
+; @param    A1      Where to return the output FSW.
+; @param    A2      Where to store the 32-bit signed integer value.
+; @param    A3      Pointer to the 80-bit value.
+;
+BEGINPROC_FASTCALL iemAImpl_fst_r80_to_i32, 12
+        PROLOGUE_3_ARGS
+        sub     xSP, 20h
+
+        fninit
+        fld     tword [A3]
+        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
+        fist    dword [A2]
+
+        fnstsw  word  [A1]
+
+        fninit
+        add     xSP, 20h
+        EPILOGUE_3_ARGS 0
+ENDPROC iemAImpl_fst_r80_to_i32
+
+
+;;
+; FPU instruction working on one 80-bit and one 32-bit signed integer value.
+;
+; @param    1       The instruction
+;
+; @param    A0      FPU context (fxsave).
+; @param    A1      Pointer to a IEMFPURESULT for the output.
+; @param    A2      Pointer to the 80-bit value.
+; @param    A3      Pointer to the 32-bit value.
+;
+%macro IEMIMPL_FPU_R80_BY_I32 1
+BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i32, 16
+        PROLOGUE_4_ARGS
+        sub     xSP, 20h
+
+        fninit
+        fld     tword [A2]
+        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
+        %1      dword [A3]
+
+        fnstsw  word  [A1 + IEMFPURESULT.FSW]
+        fnclex
+        fstp    tword [A1 + IEMFPURESULT.r80Result]
+
+        fninit
+        add     xSP, 20h
+        EPILOGUE_4_ARGS 8
+ENDPROC iemAImpl_ %+ %1 %+ _r80_by_i32
+%endmacro
+
+IEMIMPL_FPU_R80_BY_I32 fiadd
+IEMIMPL_FPU_R80_BY_I32 fimul
+IEMIMPL_FPU_R80_BY_I32 fisub
+IEMIMPL_FPU_R80_BY_I32 fisubr
+IEMIMPL_FPU_R80_BY_I32 fidiv
+IEMIMPL_FPU_R80_BY_I32 fidivr
+
+
+;;
+; FPU instruction working on one 80-bit and one 32-bit signed integer value,
+; only returning FSW.
+;
+; @param    1       The instruction
+;
+; @param    A0      FPU context (fxsave).
+; @param    A1      Where to store the output FSW.
+; @param    A2      Pointer to the 80-bit value.
+; @param    A3      Pointer to the 64-bit value.
+;
+%macro IEMIMPL_FPU_R80_BY_I32_FSW 1
+BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i32, 16
+        PROLOGUE_4_ARGS
+        sub     xSP, 20h
+
+        fninit
+        fld     tword [A2]
+        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
+        %1      dword [A3]
+
+        fnstsw  word  [A1]
+
+        fninit
+        add     xSP, 20h
+        EPILOGUE_4_ARGS 8
+ENDPROC iemAImpl_ %+ %1 %+ _r80_by_i32
+%endmacro
+
+IEMIMPL_FPU_R80_BY_I32_FSW ficom
 
 
@@ -1443 +1542 @@
 
 ;;
-; FPU instruction working on one 80-bit and one 64-bit floating point value,
+; FPU instruction working on one 80-bit and one 32-bit floating point value,
 ; only returning FSW.
 ;

trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

@@ -11329 +11329 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -11357 +11356 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -11385 +11383 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -11413 +11410 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -11436 +11432 @@
 
 /** Opcode 0xda 0xe9. */
-FNIEMOP_STUB(iemOp_fucompp);
+FNIEMOP_DEF(iemOp_fucompp)
+{
+    IEMOP_MNEMONIC("fucompp st0,stN");
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+
+    IEM_MC_BEGIN(3, 1);
+    IEM_MC_LOCAL(uint16_t,              u16Fsw);
+    IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Fsw,        u16Fsw,     0);
+    IEM_MC_ARG(PCRTFLOAT80U,            pr80Value1,                 1);
+    IEM_MC_ARG(PCRTFLOAT80U,            pr80Value2,                 2);
+
+    IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
+    IEM_MC_MAYBE_RAISE_FPU_XCPT();
+    IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, 1)
+        IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fucom_r80_by_r80, pu16Fsw, pr80Value1, pr80Value2);
+        IEM_MC_UPDATE_FSW_THEN_POP_POP(u16Fsw);
+    IEM_MC_ELSE()
+        IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP();
+    IEM_MC_ENDIF();
+    IEM_MC_ADVANCE_RIP();
+
+    IEM_MC_END();
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * Common worker for FPU instructions working on ST0 and an m32i, and storing
+ * the result in ST0.
+ *
+ * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
+ */
+FNIEMOP_DEF_2(iemOpHlpFpu_st0_m32i, uint8_t, bRm, PFNIEMAIMPLFPUI32, pfnAImpl)
+{
+    IEM_MC_BEGIN(3, 3);
+    IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
+    IEM_MC_LOCAL(IEMFPURESULT,              FpuRes);
+    IEM_MC_LOCAL(int32_t,                   i32Val2);
+    IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT,     pFpuRes,        FpuRes,     0);
+    IEM_MC_ARG(PCRTFLOAT80U,                pr80Value1,                 1);
+    IEM_MC_ARG_LOCAL_REF(int32_t const *,   pi32Val2,       i32Val2,    2);
+
+    IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+
+    IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
+    IEM_MC_MAYBE_RAISE_FPU_XCPT();
+    IEM_MC_FETCH_MEM_I32(i32Val2, pIemCpu->iEffSeg, GCPtrEffSrc);
+
+    IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
+        IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pi32Val2);
+        IEM_MC_STORE_FPU_RESULT(FpuRes, 0);
+    IEM_MC_ELSE()
+        IEM_MC_FPU_STACK_UNDERFLOW(0);
+    IEM_MC_ENDIF();
+    IEM_MC_ADVANCE_RIP();
+
+    IEM_MC_END();
+    return VINF_SUCCESS;
+}
+
+
 /** Opcode 0xda !11/0. */
-FNIEMOP_STUB_1(iemOp_fiadd_m32i,  uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fiadd_m32i,  uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fiadd m32i");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fiadd_r80_by_i32);
+}
+
+
 /** Opcode 0xda !11/1. */
-FNIEMOP_STUB_1(iemOp_fimul_m32i,  uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fimul_m32i,  uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fimul m32i");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fimul_r80_by_i32);
+}
+
+
 /** Opcode 0xda !11/2. */
-FNIEMOP_STUB_1(iemOp_ficom_m32i,  uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_ficom_m32i,  uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("ficom st0,m32i");
+
+    IEM_MC_BEGIN(3, 3);
+    IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
+    IEM_MC_LOCAL(uint16_t,                  u16Fsw);
+    IEM_MC_LOCAL(int32_t,                   i32Val2);
+    IEM_MC_ARG_LOCAL_REF(uint16_t *,        pu16Fsw,        u16Fsw,     0);
+    IEM_MC_ARG(PCRTFLOAT80U,                pr80Value1,                 1);
+    IEM_MC_ARG_LOCAL_REF(int32_t const *,   pi32Val2,       i32Val2,    2);
+
+    IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+
+    IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
+    IEM_MC_MAYBE_RAISE_FPU_XCPT();
+    IEM_MC_FETCH_MEM_I32(i32Val2, pIemCpu->iEffSeg, GCPtrEffSrc);
+
+    IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
+        IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i32, pu16Fsw, pr80Value1, pi32Val2);
+        IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pIemCpu->iEffSeg, GCPtrEffSrc);
+    IEM_MC_ELSE()
+        IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc);
+    IEM_MC_ENDIF();
+    IEM_MC_ADVANCE_RIP();
+
+    IEM_MC_END();
+    return VINF_SUCCESS;
+}
+
+
 /** Opcode 0xda !11/3. */
-FNIEMOP_STUB_1(iemOp_ficomp_m32i, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_ficomp_m32i, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("ficomp st0,m32i");
+
+    IEM_MC_BEGIN(3, 3);
+    IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
+    IEM_MC_LOCAL(uint16_t,                  u16Fsw);
+    IEM_MC_LOCAL(int32_t,                   i32Val2);
+    IEM_MC_ARG_LOCAL_REF(uint16_t *,        pu16Fsw,        u16Fsw,     0);
+    IEM_MC_ARG(PCRTFLOAT80U,                pr80Value1,                 1);
+    IEM_MC_ARG_LOCAL_REF(int32_t const *,   pi32Val2,       i32Val2,    2);
+
+    IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+
+    IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
+    IEM_MC_MAYBE_RAISE_FPU_XCPT();
+    IEM_MC_FETCH_MEM_I32(i32Val2, pIemCpu->iEffSeg, GCPtrEffSrc);
+
+    IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
+        IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i32, pu16Fsw, pr80Value1, pi32Val2);
+        IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pIemCpu->iEffSeg, GCPtrEffSrc);
+    IEM_MC_ELSE()
+        IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc);
+    IEM_MC_ENDIF();
+    IEM_MC_ADVANCE_RIP();
+
+    IEM_MC_END();
+    return VINF_SUCCESS;
+}
+
+
 /** Opcode 0xda !11/4. */
-FNIEMOP_STUB_1(iemOp_fisub_m32i,  uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fisub_m32i,  uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fisub m32i");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fisub_r80_by_i32);
+}
+
+
 /** Opcode 0xda !11/5. */
-FNIEMOP_STUB_1(iemOp_fisubr_m32i, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fisubr_m32i, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fisubr m32i");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fisubr_r80_by_i32);
+}
+
+
 /** Opcode 0xda !11/6. */
-FNIEMOP_STUB_1(iemOp_fidiv_m32i,  uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fidiv_m32i,  uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fidiv m32i");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fidiv_r80_by_i32);
+}
+
+
 /** Opcode 0xda !11/7. */
-FNIEMOP_STUB_1(iemOp_fidivr_m32i, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fidivr_m32i, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fidivr m32i");
+    return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fidivr_r80_by_i32);
+}
+
 
 /** Opcode 0xda. */
@@ -11550 +11704 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -11578 +11731 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -11606 +11758 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -11634 +11785 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
-    IEM_MC_BEGIN(0, 2);
-    IEM_MC_LOCAL(IEMFPURESULT,      FpuRes);
+    IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -810 +810 @@
 typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
 FNIEMAIMPLFPUR80FSW         iemAImpl_fcom_r80_by_r80;
+FNIEMAIMPLFPUR80FSW         iemAImpl_fucom_r80_by_r80;
 
 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
@@ -848 +849 @@
 /** @name FPU operations taking a 32-bit signed integer argument
  * @{  */
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUS32OUT,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32OUT,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
                                                      int32_t *pi32Dst, PCRTFLOAT80U pr80Value));
-typedef FNIEMAIMPLFPUS32OUT *PFNIEMAIMPLFPUS32OUT;
-
-FNIEMAIMPLFPUS32OUT iemAImpl_fpu_r80_to_i32;
-
+typedef FNIEMAIMPLFPUI32OUT *PFNIEMAIMPLFPUI32OUT;
+
+FNIEMAIMPLFPUI32OUT iemAImpl_fpu_r80_to_i32;
+
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
+typedef FNIEMAIMPLFPUI32    *PFNIEMAIMPLFPUI32;
+
+FNIEMAIMPLFPUI32    iemAImpl_fiadd_r80_by_i32;
+FNIEMAIMPLFPUI32    iemAImpl_fimul_r80_by_i32;
+FNIEMAIMPLFPUI32    iemAImpl_fisub_r80_by_i32;
+FNIEMAIMPLFPUI32    iemAImpl_fisubr_r80_by_i32;
+FNIEMAIMPLFPUI32    iemAImpl_fidiv_r80_by_i32;
+FNIEMAIMPLFPUI32    iemAImpl_fidivr_r80_by_i32;
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
+                                                   PCRTFLOAT80U pr80Val1, int32_t const *pi322Val2));
 /** @}  */
 

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -193 +193 @@
 
 #define iemAImpl_fcom_r80_by_r80        NULL
+#define iemAImpl_fucom_r80_by_r80       NULL
 #define iemAImpl_fabs_r80               NULL
 #define iemAImpl_fchs_r80               NULL
@@ -215 +216 @@
 #define iemAImpl_fxtract_r80_r80        NULL
 #define iemAImpl_fsincos_r80_r80        NULL
+
+#define iemAImpl_fiadd_r80_by_i32       NULL
+#define iemAImpl_fimul_r80_by_i32       NULL
+#define iemAImpl_fisub_r80_by_i32       NULL
+#define iemAImpl_fisubr_r80_by_i32      NULL
+#define iemAImpl_fidiv_r80_by_i32       NULL
+#define iemAImpl_fidivr_r80_by_i32      NULL
 
 #define iemCImpl_callf                  NULL
@@ -403 +411 @@
 #define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem)              do { CHK_GCPTR(a_GCPtrMem); } while (0)
 #define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem)              do { CHK_GCPTR(a_GCPtrMem); } while (0)
+#define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem)              do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int32_t, a_i32Dst); } while (0)
 #define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem)       do { CHK_GCPTR(a_GCPtrMem); } while (0)
 #define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem)              do { CHK_GCPTR(a_GCPtrMem); } while (0)
@@ -475 +484 @@
 #define IEM_MC_STORE_FPU_RESULT_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)     do { } while (0)
 #define IEM_MC_FPU_STACK_UNDERFLOW(a_iStReg)                                                    do { } while (0)
+#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff)                      do { } while (0)
 #define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStReg)                                           do { } while (0)
-#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff)                      do { } while (0)
 #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStReg, a_iEffSeg, a_GCPtrEff)             do { } while (0)
+#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(a_iStReg)                                       do { } while (0)
 #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW()                                                       do { } while (0)
 #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO()                                                   do { } while (0)
@@ -487 +497 @@
 #define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW)                                                    do { } while (0)
 #define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff)                 do { } while (0)
+#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW)                                                do { } while (0)
 #define IEM_MC_UPDATE_FPU_OPCODE_IP()                                                           do { } while (0)