Changeset 40248 in vbox for trunk/src/VBox/VMM/testcase
- Timestamp:
- Feb 24, 2012 4:12:05 PM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 76461
- Location:
- trunk/src/VBox/VMM/testcase
- Files:
-
- 2 edited
-
tstIEMCheckMc.cpp (modified) (3 diffs)
-
tstX86-1A.asm (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r40247 r40248 441 441 #define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) 442 442 #define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0) 443 #define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); } while (0) 444 #define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); } while (0) 445 #define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); } while (0) 446 #define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_u8C); } while (0) 443 #define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); } while (0) 444 #define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); } while (0) 445 #define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); } while (0) 446 #define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_u8C); } while (0) 447 #define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint16_t, a_u16C); } while (0) 448 #define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint32_t, a_u32C); } while (0) 449 #define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint64_t, a_u64C); } while (0) 450 #define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) do { CHK_TYPE(int8_t *, a_pi8Dst); CHK_CONST(int8_t, a_i8C); } while (0) 451 #define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) do { CHK_TYPE(int16_t *, a_pi16Dst); CHK_CONST(int16_t, a_i16C); } while (0) 452 #define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) do { CHK_TYPE(int32_t *, a_pi32Dst); CHK_CONST(int32_t, a_i32C); } while (0) 453 #define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) do { CHK_TYPE(int64_t *, a_pi64Dst); CHK_CONST(int64_t, a_i64C); } while (0) 454 #define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) do { CHK_TYPE(PRTFLOAT32U, a_pr32Dst); } while (0) 455 #define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) do { CHK_TYPE(PRTFLOAT64U, a_pr64Dst); } while (0) 456 #define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) do { CHK_TYPE(PRTFLOAT80U, a_pr80Dst); } while (0) 447 457 448 458 #define IEM_MC_PUSH_U16(a_u16Value) do {} while (0) … … 454 464 #define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) do { NOREF(a_fAccess); } while (0) 455 465 #define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) do {} while (0) 456 #define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do {} while (0)457 #define IEM_MC_MEM_COMMIT_AND_UNMAP_ UNLESS_FPU_XCPT(a_pvMem, a_fAccess, a_u16FSW)do {} while (0)466 #define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do {} while (0) 467 #define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) do {} while (0) 458 468 #define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); } while (0) 459 469 #define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) do {} while (0) … … 531 541 p0 = NULL; \ 532 542 if (g_fRandom) { 543 #define IEM_MC_IF_FCW_IM() if (g_fRandom) { 533 544 #define IEM_MC_ELSE() } else { 534 545 #define IEM_MC_ENDIF() } do {} while (0) -
trunk/src/VBox/VMM/testcase/tstX86-1A.asm
r40246 r40248 72 72 g_r32_QNaN: dd 07fc00000h 73 73 g_r32_QNaNMax: dd 07fffffffh 74 g_r32_NegQNaN: dd 0ffc00000h 74 75 75 76 g_r64_0dot1: dq 0.1 … … 87 88 g_r64_SNaN: dq 07ff0000000000001h 88 89 g_r64_SNaNMax: dq 07ff7ffffffffffffh 90 g_r64_NegQNaN: dq 0fff8000000000000h 89 91 g_r64_QNaN: dq 07ff8000000000000h 90 92 g_r64_QNaNMax: dq 07fffffffffffffffh … … 179 181 jmp .return 180 182 %%ok: 183 %endmacro 184 185 186 ;; 187 ; Checks if a 32-bit floating point memory value is the same as the specified 188 ; constant (also memory). 189 ; 190 ; @uses eax 191 ; @param 1 Address expression for the 32-bit floating point value 192 ; to be checked. 193 ; @param 2 The address expression of the constant. 194 ; 195 %macro CheckMemoryR32ValueConst 2 196 mov eax, [%2] 197 cmp dword [%1], eax 198 je %%ok 199 %%bad: 200 mov eax, 90000000 + __LINE__ 201 jmp .return 202 %%ok: 203 %endmacro 204 205 206 ;; 207 ; Checks if a 80-bit floating point memory value is the same as the specified 208 ; constant (also memory). 209 ; 210 ; @uses eax 211 ; @param 1 Address expression for the FXSAVE image. 212 ; @param 2 The address expression of the constant. 213 ; 214 %macro CheckMemoryR80ValueConst 2 215 mov eax, [%2] 216 cmp dword [%1], eax 217 je %%ok1 218 %%bad: 219 mov eax, 92000000 + __LINE__ 220 jmp .return 221 %%ok1: 222 mov eax, [4 + %2] 223 cmp dword [%1 + 4], eax 224 jne %%bad 225 mov ax, [8 + %2] 226 cmp word [%1 + 8], ax 227 jne %%bad 181 228 %endmacro 182 229 … … 3064 3111 FxSaveCheckStNValueConst xSP, 1, REF(g_r80_3dot2) 3065 3112 FxSaveCheckStNValueConst xSP, 2, REF(g_r80_0dot1) 3066 3113 %endif 3114 3115 ; 3116 ; FSTP M32R, ST0 3117 ; 3118 SetSubTest "FSTP M32R, ST0" 3119 3120 mov xBX, [REF_EXTERN(g_pbEfExecPage)] 3121 lea xBX, [xBX + PAGE_SIZE - 4] 3122 3123 ; ## Normal operation. ## 3124 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3125 fld dword [REF(g_r32_Ten)] 3126 FpuCheckOpcodeCsIp { fstp dword [xBX] } 3127 FxSaveCheckFSW xSP, 0, 0 3128 FxSaveCheckSt0Empty xSP 3129 CheckMemoryR32ValueConst xBX, REF(g_r32_Ten) 3130 3131 ; ## Masked exceptions. ## 3132 3133 ; Masked stack underflow. 3134 fninit 3135 FpuCheckOpcodeCsIp { fstp dword [xBX] } 3136 FxSaveCheckFSW xSP, X86_FSW_IE | X86_FSW_SF, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3137 CheckMemoryR32ValueConst xBX, REF(g_r32_NegQNaN) 3138 3139 fninit 3140 fld tword [REF(g_r80_0dot1)] 3141 fld tword [REF(g_r80_3dot2)] 3142 fld tword [REF(g_r80_Ten)] 3143 ffree st0 3144 FpuCheckOpcodeCsIp { fstp dword [xBX] } 3145 FxSaveCheckFSW xSP, X86_FSW_IE | X86_FSW_SF, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3146 CheckMemoryR32ValueConst xBX, REF(g_r32_NegQNaN) 3147 FxSaveCheckStNValueConst xSP, 0, REF(g_r80_3dot2) 3148 FxSaveCheckStNValueConst xSP, 1, REF(g_r80_0dot1) 3149 3150 ; Masked #IA caused by SNaN. 3151 fninit 3152 fld tword [REF(g_r80_SNaN)] 3153 FpuCheckOpcodeCsIp { fstp dword [xBX] } 3154 FxSaveCheckFSW xSP, X86_FSW_IE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3155 CheckMemoryR32ValueConst xBX, REF(g_r32_QNaN) 3156 3157 ; Masked #U caused by a denormal value. 3158 fninit 3159 fld tword [REF(g_r80_DnMin)] 3160 FpuCheckOpcodeCsIp { fstp dword [xBX] } 3161 FxSaveCheckFSW xSP, X86_FSW_UE | X86_FSW_PE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3162 CheckMemoryR32ValueConst xBX, REF(g_r32_Zero) 3163 3164 ; Masked #P caused by a decimal value. 3165 fninit 3166 fld tword [REF(g_r80_3dot2)] 3167 FpuCheckOpcodeCsIp { fstp dword [xBX] } 3168 FxSaveCheckFSW xSP, X86_FSW_C1 | X86_FSW_PE, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3169 CheckMemoryR32ValueConst xBX, REF(g_r32_3dot2) 3170 3171 ; ## Unmasked exceptions. ## 3172 3173 ; Stack underflow - nothing stored or popped. 3174 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3175 mov dword [xBX], 0xffeeddcc 3176 FpuTrapOpcodeCsIp { fstp dword [xBX] } 3177 FxSaveCheckFSW xSP, X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3178 CheckMemoryValue dword, xBX, 0xffeeddcc 3179 3180 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3181 fld tword [REF(g_r80_0dot1)] 3182 fld tword [REF(g_r80_3dot2)] 3183 fld tword [REF(g_r80_Ten)] 3184 ffree st0 3185 mov dword [xBX], 0xffeeddcc 3186 FpuTrapOpcodeCsIp { fstp dword [xBX] } 3187 FxSaveCheckFSW xSP, X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3188 CheckMemoryValue dword, xBX, 0xffeeddcc 3189 FxSaveCheckStNEmpty xSP, 0 3190 FxSaveCheckStNValueConst xSP, 1, REF(g_r80_3dot2) 3191 FxSaveCheckStNValueConst xSP, 2, REF(g_r80_0dot1) 3192 3193 ; #IA caused by SNaN. 3194 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3195 fld tword [REF(g_r80_SNaN)] 3196 mov dword [xBX], 0xffeeddcc 3197 FpuTrapOpcodeCsIp { fstp dword [xBX] } 3198 FxSaveCheckFSW xSP, X86_FSW_IE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3199 CheckMemoryValue dword, xBX, 0xffeeddcc 3200 3201 ; #U caused by a denormal value - nothing written 3202 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3203 fld tword [REF(g_r80_DnMin)] 3204 mov dword [xBX], 0xffeeddcc 3205 FpuTrapOpcodeCsIp { fstp dword [xBX] } 3206 FxSaveCheckFSW xSP, X86_FSW_UE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3207 CheckMemoryValue dword, xBX, 0xffeeddcc 3208 3209 ; #U caused by a small value - nothing written 3210 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3211 fld tword [REF(g_r80_Min)] 3212 mov dword [xBX], 0xffeeddcc 3213 FpuTrapOpcodeCsIp { fstp dword [xBX] } 3214 FxSaveCheckFSW xSP, X86_FSW_UE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3215 CheckMemoryValue dword, xBX, 0xffeeddcc 3216 3217 ; #O caused by a small value - nothing written 3218 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3219 fld tword [REF(g_r80_Max)] 3220 mov dword [xBX], 0xffeeddcc 3221 FpuTrapOpcodeCsIp { fstp dword [xBX] } 3222 FxSaveCheckFSW xSP, X86_FSW_OE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3223 CheckMemoryValue dword, xBX, 0xffeeddcc 3224 3225 ; #P caused by a decimal value - rounded value is written just like if it was masked. 3226 FpuInitWithCW X86_FCW_PC_64 | X86_FCW_RC_NEAREST 3227 fld tword [REF(g_r80_3dot2)] 3228 mov dword [xBX], 0xffeeddcc 3229 FpuTrapOpcodeCsIp { fstp dword [xBX] } 3230 FxSaveCheckFSW xSP, X86_FSW_C1 | X86_FSW_PE | X86_FSW_ES | X86_FSW_B, X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3 3231 CheckMemoryR32ValueConst xBX, REF(g_r32_3dot2) 3232 3233 %if 0 ;; @todo implement me 3067 3234 ; 3068 3235 ; FISTP M32I, ST0 … … 3115 3282 FxSaveCheckStNValueConst xSP, 1, REF(g_r80_3dot2) 3116 3283 FxSaveCheckStNValueConst xSP, 2, REF(g_r80_0dot1) 3117 3284 %endif 3285 %if 0 3118 3286 ; 3119 3287 ; FPTAN - calc, store ST0, push 1.0. … … 3149 3317 3150 3318 ;; @todo Finish FPTAN testcase. 3151 %endif3152 3319 3153 3320 ; … … 3234 3401 3235 3402 ;; @todo Finish FCMOVB testcase. 3403 %endif 3236 3404 3237 3405
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