Changeset 40251 in vbox

Timestamp:

Feb 24, 2012 9:24:23 PM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

76465

Message:

fcomi, fcomip, fucomi and fucomip.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl.asm (modified) (1 diff)
• VMMAll/IEMAllCImpl.cpp.h (modified) (1 diff)
• VMMAll/IEMAllInstructions.cpp.h (modified) (2 diffs)
• include/IEMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -2055 +2055 @@
 
 ;;
+; FPU instruction working on two 80-bit floating point values,
+; returning FSW and EFLAGS (eax).
+;
+; @param    1       The instruction
+;
+; @returns  EFLAGS in EAX.
+; @param    A0      FPU context (fxsave).
+; @param    A1      Pointer to a uint16_t for the resulting FSW.
+; @param    A2      Pointer to the first 80-bit value.
+; @param    A3      Pointer to the second 80-bit value.
+;
+%macro IEMIMPL_FPU_R80_BY_R80_EFL 1
+BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
+        PROLOGUE_4_ARGS
+        sub     xSP, 20h
+
+        fninit
+        fld     tword [A3]
+        fld     tword [A2]
+        FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
+        %1      st1
+
+        fnstsw  word  [A1]
+        pushf
+        pop     xAX
+
+        fninit
+        add     xSP, 20h
+        EPILOGUE_4_ARGS 8
+ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
+%endmacro
+
+IEMIMPL_FPU_R80_BY_R80_EFL fcomi
+IEMIMPL_FPU_R80_BY_R80_EFL fucomi
+
+
+;;
 ; FPU instruction working on one 80-bit floating point value.
 ;

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -4341 +4341 @@
     pCtx->fpu.FSW = u16Fsw;
 
+    iemRegAddToRip(pIemCpu, cbInstr);
     return VINF_SUCCESS;
 }
 
 
+/**
+ * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
+ *
+ * @param   cToAdd              1 or 7.
+ */
+IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
+{
+    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
+    Assert(iStReg < 8);
+
+    /*
+     * Raise exceptions.
+     */
+    if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
+        return iemRaiseDeviceNotAvailable(pIemCpu);
+    uint16_t u16Fsw = pCtx->fpu.FSW;
+    if (u16Fsw & X86_FSW_ES)
+        return iemRaiseMathFault(pIemCpu);
+
+    /*
+     * Check if any of the register accesses causes #SF + #IA.
+     */
+    unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
+    unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
+    if ((pCtx->fpu.FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
+    {
+        uint32_t u32Eflags = pfnAImpl(&pCtx->fpu, &u16Fsw, &pCtx->fpu.aRegs[0].r80, &pCtx->fpu.aRegs[iStReg].r80);
+        pCtx->fpu.FSW &= ~X86_FSW_C1;
+        pCtx->fpu.FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
+        if (   !(u16Fsw & X86_FSW_IE)
+            || (pCtx->fpu.FCW & X86_FCW_IM) )
+        {
+            pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
+            pCtx->eflags.u |= pCtx->eflags.u & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
+        }
+    }
+    else if (pCtx->fpu.FCW & X86_FCW_IM)
+    {
+        /* Masked underflow. */
+        pCtx->fpu.FSW &= ~X86_FSW_C1;
+        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF;
+        pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
+        pCtx->eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
+    }
+    else
+    {
+        /* Raise underflow - don't touch EFLAGS or TOP. */
+        pCtx->fpu.FSW &= ~X86_FSW_C1;
+        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
+        fPop = false;
+    }
+
+    /*
+     * Pop if necessary.
+     */
+    if (fPop)
+    {
+        pCtx->fpu.FTW &= ~RT_BIT(iReg1);
+        pCtx->fpu.FSW &= X86_FSW_TOP_MASK;
+        pCtx->fpu.FSW |= ((iReg1 + 7) & X86_FSW_TOP_SMASK) << X86_FSW_TOP_SHIFT;
+    }
+
+    iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
+    iemRegAddToRip(pIemCpu, cbInstr);
+    return VINF_SUCCESS;
+}
+
 /** @} */
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

@@ -12050 +12050 @@
 
 /** Opcode 0xdb 11/5. */
-FNIEMOP_STUB_1(iemOp_fucomi_stN, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fucomi_stN, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fucomi st0,stN");
+    return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fucomi_r80_by_r80, false /*fPop*/);
+}
+
 
 /** Opcode 0xdb 11/6. */
-FNIEMOP_STUB_1(iemOp_fcomi_stN,  uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fcomi_stN,  uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fcomi st0,stN");
+    return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fcomi_r80_by_r80, false /*fPop*/);
+}
 
 
@@ -12595 +12604 @@
 
 /** Opcode 0xdf 11/5. */
-FNIEMOP_STUB_1(iemOp_fucomip_st0_stN, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fucomip_st0_stN, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fcomip st0,stN");
+    return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fcomi_r80_by_r80, true /*fPop*/);
+}
+
 
 /** Opcode 0xdf 11/6. */
-FNIEMOP_STUB_1(iemOp_fcomip_st0_stN,  uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_fcomip_st0_stN,  uint8_t, bRm)
+{
+    IEMOP_MNEMONIC("fcomip st0,stN");
+    return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fcomi_r80_by_r80, true /*fPop*/);
+}
+
 
 /** Opcode 0xdf !11/0. */

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -812 +812 @@
 FNIEMAIMPLFPUR80FSW         iemAImpl_fucom_r80_by_r80;
 
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
+                                                          PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
+typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
+FNIEMAIMPLFPUR80EFL         iemAImpl_fcomi_r80_by_r80;
+FNIEMAIMPLFPUR80EFL         iemAImpl_fucomi_r80_by_r80;
+
 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
 typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;