Changeset 40280 in vbox for trunk/src/VBox/Devices/PC

Timestamp:

Feb 28, 2012 7:47:00 PM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

76509

Message:

Corrected a bunch of HC and GC uses in status codes.

Location:

trunk/src/VBox/Devices/PC

Files:

• DevACPI.cpp (modified) (1 diff)
• DevAPIC.cpp (modified) (4 diffs)
• DevHPET.cpp (modified) (19 diffs)
• DevIoApic.cpp (modified) (2 diffs)
• DevPIC.cpp (modified) (4 diffs)
• DevPit-i8254.cpp (modified) (8 diffs)

trunk/src/VBox/Devices/PC/DevACPI.cpp

@@ -1616 +1616 @@
      * make sure we get a reliable time from the clock.
      */
-    int rc = TMTimerLock(pThis->CTX_SUFF(pPmTimer), VINF_IOM_HC_IOPORT_READ);
+    int rc = TMTimerLock(pThis->CTX_SUFF(pPmTimer), VINF_IOM_R3_IOPORT_READ);
     if (rc == VINF_SUCCESS)
     {

trunk/src/VBox/Devices/PC/DevAPIC.cpp

@@ -573 +573 @@
 #else
             /* We shall send init IPI only in R3. */
-            return VINF_IOM_HC_MMIO_READ_WRITE;
+            return VINF_IOM_R3_MMIO_READ_WRITE;
 #endif /* IN_RING3 */
 
@@ -1415 +1415 @@
             /* We shall send SIPI only in R3, R0 calls should be
                rescheduled to R3 */
-            return VINF_IOM_HC_MMIO_WRITE;
+            return VINF_IOM_R3_MMIO_WRITE;
 # endif
     }
@@ -1845 +1845 @@
             uint64_t u64Value = 0;
             int rc = apicReadRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, &u64Value,
-                                      VINF_IOM_HC_MMIO_READ, false /*fMsr*/);
+                                      VINF_IOM_R3_MMIO_READ, false /*fMsr*/);
             *(uint32_t *)pv = (uint32_t)u64Value;
             return rc;
@@ -1878 +1878 @@
             /* It does its own locking. */
             return apicWriteRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, *(uint32_t const *)pv,
-                                     VINF_IOM_HC_MMIO_WRITE, false /*fMsr*/);
+                                     VINF_IOM_R3_MMIO_WRITE, false /*fMsr*/);
 
         default:

trunk/src/VBox/Devices/PC/DevHPET.cpp

@@ -524 +524 @@
         case HPET_TN_CFG:
         {
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, u32NewValue));
             uint64_t const iOldValue = (uint32_t)pHpetTimer->u64Config;
@@ -565 +565 @@
         case HPET_TN_CMP: /* lower bits of comparator register */
         {
-            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             Log(("write HPET_TN_CMP on %d: %#x\n", iTimerNo, u32NewValue));
 
@@ -585 +585 @@
         case HPET_TN_CMP + 4: /* upper bits of comparator register */
         {
-            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             Log(("write HPET_TN_CMP + 4 on %d: %#x\n", iTimerNo, u32NewValue));
             if (!hpet32bitTimer(pHpetTimer))
@@ -650 +650 @@
     {
         case HPET_ID:
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
             u32Value = pThis->u32Capabilities;
             DEVHPET_UNLOCK(pThis);
@@ -657 +657 @@
 
         case HPET_PERIOD:
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
             u32Value = pThis->u32Period;
             DEVHPET_UNLOCK(pThis);
@@ -664 +664 @@
 
         case HPET_CFG:
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
             u32Value = (uint32_t)pThis->u64HpetConfig;
             DEVHPET_UNLOCK(pThis);
@@ -671 +671 @@
 
         case HPET_CFG + 4:
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
             u32Value = (uint32_t)(pThis->u64HpetConfig >> 32);
             DEVHPET_UNLOCK(pThis);
@@ -680 +680 @@
         case HPET_COUNTER + 4:
         {
-            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
 
             uint64_t u64Ticks;
@@ -698 +698 @@
 
         case HPET_STATUS:
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
             u32Value = (uint32_t)pThis->u64Isr;
             DEVHPET_UNLOCK(pThis);
@@ -743 +743 @@
         case HPET_CFG:
         {
-            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             uint32_t const iOldValue = (uint32_t)(pThis->u64HpetConfig);
             Log(("write HPET_CFG: %x (old %x)\n", u32NewValue, iOldValue));
@@ -758 +758 @@
                 if (rc != VINF_SUCCESS)
 #else
-                rc = VINF_IOM_HC_MMIO_WRITE;
+                rc = VINF_IOM_R3_MMIO_WRITE;
 #endif
                 {
@@ -793 +793 @@
         case HPET_CFG + 4:
         {
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             pThis->u64HpetConfig = hpetUpdateMasked((uint64_t)u32NewValue << 32,
                                                     pThis->u64HpetConfig,
@@ -804 +804 @@
         case HPET_STATUS:
         {
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             /* Clear ISR for all set bits in u32NewValue, see p. 14 of the HPET spec. */
             pThis->u64Isr &= ~((uint64_t)u32NewValue);
@@ -826 +826 @@
         case HPET_COUNTER:
         {
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             pThis->u64HpetCounter = RT_MAKE_U64(u32NewValue, pThis->u64HpetCounter);
             Log(("write HPET_COUNTER: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
@@ -835 +835 @@
         case HPET_COUNTER + 4:
         {
-            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             pThis->u64HpetCounter = RT_MAKE_U64(pThis->u64HpetCounter, u32NewValue);
             Log(("write HPET_COUNTER + 4: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
@@ -875 +875 @@
             if (idxReg >= 0x100 && idxReg < 0x400)
             {
-                DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+                DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
                 rc = hpetTimerRegRead32(pThis,
                                         (idxReg - 0x100) / 0x20,
@@ -902 +902 @@
                 /* When reading HPET counter we must read it in a single read,
                    to avoid unexpected time jumps on 32-bit overflow. */
-                DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+                DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
                 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
                     pValue->u = hpetGetTicks(pThis);
@@ -911 +911 @@
             else
             {
-                DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
+                DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
                 if (idxReg >= 0x100 && idxReg < 0x400)
                 {
@@ -981 +981 @@
 
             /* Split the access and rely on the locking to prevent trouble. */
-            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
+            DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
             RTUINT64U uValue;
             uValue.u = *(uint64_t const *)pv;

trunk/src/VBox/Devices/PC/DevIoApic.cpp

@@ -325 +325 @@
 {
     IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *);
-    IOAPIC_LOCK(pThis, VINF_IOM_HC_MMIO_READ);
+    IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_READ);
 
     STAM_COUNTER_INC(&CTXSUFF(pThis->StatMMIORead));
@@ -356 +356 @@
 
     STAM_COUNTER_INC(&CTXSUFF(pThis->StatMMIOWrite));
-    IOAPIC_LOCK(pThis, VINF_IOM_HC_MMIO_WRITE);
+    IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
     switch (cb)
     {

trunk/src/VBox/Devices/PC/DevPIC.cpp

@@ -671 +671 @@
     {
         int rc;
-        PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_READ);
+        PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_READ);
         *pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
         PIC_UNLOCK(pThis);
@@ -700 +700 @@
     {
         int rc;
-        PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_WRITE);
+        PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_WRITE);
         rc = pic_ioport_write(&pThis->aPics[iPic], Port, u32);
         PIC_UNLOCK(pThis);
@@ -725 +725 @@
     {
         PicState *s = (PicState*)pvUser;
-        PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
+        PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_READ);
         *pu32 = s->elcr;
         PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
@@ -750 +750 @@
     {
         PicState *s = (PicState*)pvUser;
-        PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
+        PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_WRITE);
         s->elcr = u32 & s->elcr_mask;
         PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));

trunk/src/VBox/Devices/PC/DevPit-i8254.cpp

@@ -577 +577 @@
     PITChannelState *s = &pit->channels[Port];
 
-    DEVPIT_LOCK_RETURN(pit, VINF_IOM_HC_IOPORT_READ);
+    DEVPIT_LOCK_RETURN(pit, VINF_IOM_R3_IOPORT_READ);
     if (s->status_latched)
     {
@@ -607 +607 @@
     {
         DEVPIT_UNLOCK(pit);
-        DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_HC_IOPORT_READ);
+        DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_READ);
         int count;
         switch (s->read_state)
@@ -685 +685 @@
         {
             /* read-back command */
-            DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_HC_IOPORT_WRITE);
+            DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
             for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
             {
@@ -713 +713 @@
             if (access == 0)
             {
-                DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_HC_IOPORT_WRITE);
+                DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
                 pit_latch_count(s);
                 DEVPIT_UNLOCK_BOTH(pit);
@@ -719 +719 @@
             else
             {
-                DEVPIT_LOCK_RETURN(pit, VINF_IOM_HC_IOPORT_WRITE);
+                DEVPIT_LOCK_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
                 s->rw_mode = access;
                 s->read_state = access;
@@ -736 +736 @@
         /** @todo There is no reason not to do this in all contexts these
          *        days... */
-        return VINF_IOM_HC_IOPORT_WRITE;
+        return VINF_IOM_R3_IOPORT_WRITE;
 #else /* IN_RING3 */
         /*
@@ -743 +743 @@
         PITChannelState *s = &pit->channels[Port];
         uint8_t const write_state = s->write_state;
-        DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_HC_IOPORT_WRITE);
+        DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
         switch (s->write_state)
         {
@@ -786 +786 @@
     {
         PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
-        DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_IOPORT_READ);
+        DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
 
         const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));